1. Chapter 8: Programmable Processors
Digital Design
Chapter 8:
Programmable Processors
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
Copyright © 2007 Frank Vahid
Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors may obtain PowerPoint source or obtain special use permissions from Wiley – see for information.

2. Introduction a tap a si r t n o c o t g
8.1
Introduction
Programmable (general-purpose) processor
Mass-produced, then programmed to implement different processing tasks
Well-known common programmable processors: Pentium, Sparc, PowerPC
Lesser-known but still common: ARM, MIPS, 8051, PIC
Low-cost embedded processors found in cell phones, blinking shoes, etc.
Instructive to design a very simple programmable processor
Real processors can be much more complex a
Seatbelt
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program O
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ams
3-tap FIR filter
program e 3 a 2
tap
Seatbelt warning
light single-purpose
processor 1 si a I
nstru c
tion
memo r y I 2x 4 D a
ta memo r
y D t r
x(t) x( t
-1) x( t
-2) n o c c0 c1 c2 t o
n-bit x t0 x t1 x t2 PC I R 2x 1 g * * * R e g is t
er file RF C o n t r
oller + + r eg A L U
Control unit
Datapath
3-tap FIR filter
single-purpose processor
General-purpose processor
Note: Slides with animation are denoted with a small red "a" near the animated items

3. Basic Architecture Processing generally consists of:
8.2
Basic Architecture
Processing generally consists of:
Loading some data
Transforming that data
Storing that data
Basic datapath: Useful circuit in a programmable processor
Can read/write data memory, where main data exists
Has register file to hold data locally
Has ALU to transform local data
someh o w c
onne c t ed t
o the D a
ta memo r
y D
outside w o r ld
n-bit 2x 1 a
tap si a R e g is t
er file RF t r n o c o t A L U g
Datapath

4. Basic Datapath Operations
Load operation: Load data from data memory to RF
ALU operation: Transforms data by passing one or two RF register values through ALU, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF.
Store operation: Stores RF register value back into data memory
Each operation can be done in one clock cycle
Data memory D
Data memory D
Data memory D
Store operation
Load operation
ALU operation
n-bit
n-bit
n-bit 2x 1 2x 1 2x 1 a
Register file RF
Register file RF
Register file RF
ALU
ALU
ALU

5. Basic Datapath Operations
Q: Which are valid single-cycle operations for given datapath?
Move D[1] to RF[1] (i.e., RF[1] = D[1])
A: YES – That's a load operation
Store RF[1] to D[9] and store RF[2] to D[10]
A: NO – Requires two separate store operations
Add D[0] plus D[1], store result in D[9]
A: NO – ALU operation (ADD) only works with RF. Requires two load operations (e.g., RF[0]=D[0]; RF[1]=D[1], an ALU operation (e.g., RF[2]=RF[0]+RF[1]), and a store operation (e.g., D[9]=RF[2]) a
Register file RF
Data memory D
ALU
n-bit 2x 1
Load operation
ALU operation
Store operation

6. Basic Architecture – Control Unit
D[9] = D[0] + D[1] – requires a sequence of four datapath operations:
0: RF[0] = D[0]
1: RF[1] = D[1]
2: RF[2] = RF[0] + RF[1]
3: D[9] = RF[2]
Each operation is an instruction
Sequence of instructions – program
Looks cumbersome, but that's the world of programmable processors – Decomposing desired computations into processor-supported operations
Store program in Instruction memory
Control unit reads each instruction and executes it on the datapath
PC: Program counter – address of current instruction
IR: Instruction register – current instruction
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Data memory D a
n-bit 2 x 1 PC IR
Register file RF
Controller
ALU
signals to control the datapath
Control unit
Datapath

7. Basic Architecture – Control Unit
To carry out each instruction, the control unit must:
Fetch – Read instruction from inst. mem.
Decode – Determine the operation and operands of the instruction
Execute – Carry out the instruction's operation using the datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] ( a )
Fetch
RF[0]=D[0]
Instruction memory I
Control unit PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] 1 ( b )
Controller
Decode
Register file RF
Data memory D
D[0]: 99
ALU
n-bit 2 x 1
Datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
RF[0]=D[0] ( c )
Execute
-> 1
RF[0]=D[0]
signals to control the datapath
R[0]: ??
 99
signals to control the datapath a
"load"
signals to control the datapath
signals to control the datapath

8. Basic Architecture – Control Unit
To carry out each instruction, the control unit must:
Fetch – Read instruction from inst. mem.
Decode – Determine the operation and operands of the instruction
Execute – Carry out the instruction's operation using the datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] ( a )
Fetch
RF[1]=D[1]
Instruction memory I
Control unit PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] 2 ( b )
Controller
Decode
Register file RF
Data memory D
D[1]: 102
ALU
n-bit 2 x 1
Datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
RF[1]=D[1] ( c )
Execute 1
-> 2
RF[1]=D[1}
signals to control the datapath
R[1]: ??
 102
signals to control the datapath a
"load"
signals to control the datapath
signals to control the datapath

9. Basic Architecture – Control Unit
To carry out each instruction, the control unit must:
Fetch – Read instruction from inst. mem.
Decode – Determine the operation and operands of the instruction
Execute – Carry out the instruction's operation using the datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] ( a )
Fetch
RF[2]=RF[0]+RF[1]
Instruction memory I
Control unit PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] 3 ( b )
Controller
Decode
Register file RF
Data memory D
ALU
n-bit 2 x 1
Datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
RF[2]=RF[0]+RF[1] 3 ( c )
Execute
201 2
-> 3
RF[2]=RF[0]+RF[1]
signals to control the datapath
R[2]: ??
 201
signals to control the datapath 99
102 a
"ALU (add)"
signals to control the datapath
signals to control the datapath

10. Basic Architecture – Control Unit
To carry out each instruction, the control unit must:
Fetch – Read instruction from inst. mem.
Decode – Determine the operation and operands of the instruction
Execute – Carry out the instruction's operation using the datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] ( a )
Fetch
D[9]=RF[2]
Instruction memory I
Control unit PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2] 4 ( b )
Controller
Decode
Register file RF
Data memory D
ALU
n-bit 2 x 1
Datapath
Instruction memory I
Control unit
Controller PC R
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
D[9]=RF[2] 4 ( c )
D[9]=??
 201 3
-> 4
D[9]=RF[2]
signals to control the datapath
R[2]: 201
signals to control the datapath a
"store"
signals to control the datapath
signals to control the datapath
Execute

11. Basic Architecture – Control Unit
Register file RF
Data memory D
ALU
n-bit 2 x 1
Datapath
Instruction memory I
Control unit
Controller PC IR
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
signals to control the datapath
signals to control the datapath
signals to control the datapath
signals to control the datapath

12. Creating a Sequence of Instructions
Q: Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2] on earlier-introduced processor
A1: One possible sequence
First load data memory locations into register file
R[3] = D[0]
R[4] = D[1]
R[2] = D[2]
(Note arbitrary register locations)
A2: Alternative sequence
First load D[0] and D[1] and add them
R[1] = D[0]
R[2] = D[1]
R[1] = R[1] + R[2] a a
Next, load D[2] and add
R[2] = D[2]
R[1] = R[1] + R[2]
Next, perform the additions
R[1] = R[3] + R[4]
R[1] = R[1] + R[2]
Finally, store result
D[3] = R[1]
Finally, store result
D[3] = R[1]

13. Number of Cycles
Q: How many cycles are needed to execute six instructions using the earlier-described processor?
A: Each instruction requires 3 cycles – 1 to fetch, 1 to decode, and 1 to execute
Thus, 6 instr * 3 cycles/instr = 18 cycles a

14. Three-Instruction Programmable Processor
8.3
Three-Instruction Programmable Processor
Instruction Set – List of allowable instructions and their representation in memory, e.g.,
Load instruction—0000 r3r2r1r0 d7d6d5d4d3d2d1d0
Store instruction—0001 r3r2r1r0 d7d6d5d4d3d2d1d0
Add instruction—0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
Instruction memory I 0: 1: 2: 3:
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2}
Desired program a a
Instructions in 0s and 1s – machine code
opcode
operands

15. Program for Three-Instruction Processor
Desired program
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2}
Computes
D[9] =
D[0] +
D[1]
Instruction memory I 0:
Data memory D 1: 2: 3:
n-bit 2 × 1 PC I R
Register file RF
Controller
ALU
signals to control the datapath
Control unit
Datapath

16. Program for Three-Instruction Processor
Another example program in machine code
Compute D[5] = D[5] + D[6] + D[7]
Load instruction—0000 r3r2r1r0 d7d6d5d4d3d2d1d0
Store instruction—0001 r3r2r1r0 d7d6d5d4d3d2d1d0
Add instruction—0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
signals to control the datapath

17. Assembly Code Machine code (0s and 1s) hard to work with
Assembly code – Uses mnemonics
Load instruction—MOV Ra, d
specifies the operation RF[a]=D[d]. a must be 0,1, ..., or 15—so R0 means RF[0], R1 means RF[1], etc. d must be 0, 1, ..., 255
• Store instruction—MOV d, Ra
specifies the operation D[d]=RF[a]
• Add instruction—ADD Ra, Rb, Rc
specifies the operation RF[a]=RF[b]+RF[c]
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Desired program
0: MOV R0, 0
1: MOV R1, 1
2: ADD R2, R0, R1
3: MOV 9, R2 0: 1: 2: 3:
machine code
assembly code

18. Control-Unit and Datapath for Three-Instruction Processor
To design the processor, we can begin with a high-level state machine description of the processor's behavior
Init
IR=I[PC]
Fetch
PC=0
PC=PC+1
Decode
op=0000
op=0001
op=0010
Load
Store
Add
RF[ra]=D[d]
D[d]=RF[ra]
RF[ra] =
RF[rb]+
RF[rc]

19. Control-Unit and Datapath for Three-Instruction Processor
Create detailed connections among components
D_addr 8
addr rd
data I
addr D
D_rd 16 rd
D_wr
256 x 16 16 wr
W_data
R_data PC I R
clr up Id
Init 16
IR=I[PC] 16
Fetch
PC=0
PC=PC+1 1
RF_s
16-bit
PC_clr
PC_inc I
_rd I
R_ld s 2 x 1 16
Decode
RF_W_addr 4
W_data
op=0000
op=0001
op=0010
W_addr
RF_W_wr
W_wr
RF_Rp_addr 4
Rp_addr
Controller
RF_Rp_rd
Load
Store 16 x 16
Add
Rp_rd
RF_Rq_addr 4 RF
RF[ra]=D[d]
D[d]=RF[ra]
RF[ra] =
Rq_addr
RF_Rq_rd
RF[rb]+
Rq_rd
RF[rc] 16
Rp_data
Rq_data
alu_s0 16 16 A B s0
ALU
Control unit
Datapath 16

20. Control-Unit and Datapath for Three-Instruction Processor
Convert high-level state machine description of entire processor to FSM description of controller that uses datapath and other components to achieve same behavior PC
clr up 16 I R Id
data rd
addr
Controller
Control unit
Datapath
RF_W_wr
RF_Rp_addr
RF_Rq_addr
RF_Rq_rd
RF_Rp_rd
RF_W_addr
D_addr 8
D_rd
D_wr
RF_s
alu_s0 D wr
256 x RF
16-bit 2 1
W_data
R_data
Rp_data
Rq_data
W_addr
W_wr
Rp_addr
Rp_rd
Rq_addr
Rq_rd s A B s0
ALU 4
Fetch
Decode
Init
PC=0
PC_ clr=1
Store I R=
[PC] PC=PC+1
_rd=1 PC_inc=1
R_ld=1
Load
Add
Execute
states
RF[ra] = RF[rb]+
RF[rc]
D[d]=RF[ra]
RF[ra]=D[d]
op=0000
op=0001
op=0010
D_addr=d
D_wr=1
RF_s=X
RF_Rp_addr=ra
RF_Rp_rd=1
RF_Rp_addr=rb
RF_s=0
RF_Rq_addr=rc
RF_Rq _rd=1
RF_W_addr=ra
RF_W_wr=1
alu_s0=1
D_rd=1
RF_s=1 a
PC_clr
PC_inc I
_rd I
R_ld

21. A Six-Instruction Programmable Processor
8.4
A Six-Instruction Programmable Processor
Let's add three more instructions:
Load-constant instruction—0011 r3r2r1r0 c7c6c5c4c3c2c1c0
MOV Ra, #c—specifies the operation RF[a]=c
Subtract instruction—0100 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
SUB Ra, Rb, Rc—specifies the operation RF[a]=RF[b] – RF[c]
Jump-if-zero instruction—0101 ra3ra2ra1ra0 o7o6o5o4o3o2o1o0
JMPZ Ra, offset—specifies the operation PC = PC + offset if RF[a] is 0

22. Extending the Control-Unit and Datapath
1: The load constant instruction requires that the register file be able to load data from IR[7..0], in addition to data from data memory or the ALU output. Thus, we widen the register file’s multiplexer from 2x1 to 3x1, add another mux control signal, and also create a new signal coming from the controller labeled RF_W_data, which will connect with IR[7..0].
2: The subtract instruction requires that we use an ALU capable of subtraction, so we add another ALU control signal.
3: The jump-if-zero instruction requires that we be able to detect if a register is zero, and that we be able to add IR[7..0] to the PC.
3a: We insert a datapath component to detect if the register file’s Rp read port is all zeros (that component would just be a NOR gate).
3b: We also upgrade the PC register so it can be loaded with PC plus IR[7..0]. The adder used for this also subtracts 1 from the sum, to compensate for the fact that the Fetch state already added 1 to the PC.
Datapath
RF_Rp_addr
RF_Rq_addr
RF_Rp_zero
RF_W_addr
D_addr
D_rd
D_wr
RF_s1
RF_W_data
RF_s0
alu_s1
alu_s0
addr D rd wr
256 x 16 RF
16-bit 3 1
W_data
R_data
Rp_data
Rq_data
W_addr
W_wr
Rp_addr
Rp_rd
Rq_addr
Rq_rd s1 s0 2 A B
ALU 4 3a =0 8
ALU operation
pass A through
A+B
A-B PC
clr ld up I R Id
data
Controller
Control unit
a+b-1 * + 3b
IR[7..0]
_rd I
PC_ld
PC_clr
PC_inc
IR_ld

23. Controller FSM for the Six-Instruction Processor
Init I
_rd=1
Fetch
PC_inc=1
PC_clr=1 I
R_ld=1
Decode
op=0000
op=0001
op=0010
op=0011
op=0100
op=0101
Load-
Load
Store
Add
Subtract
Jump-if-zero
constant
D_addr=d
D_addr=d
RF_Rp_addr=rb
RF_s1=1
RF_Rp_addr=rb
RF_Rp_addr=ra
D_rd=1
D_wr=1
RF_Rp_rd=1
RF_s0=0
RF_Rp_rd=1
RF_Rp_zero
RF_Rp_rd=1
RF_s1 =
RF_s1 = X
RF_s1 =
RF_W_addr=ra
RF_s1=0 R F _ s0 = 1
RF_s0 = X
RF_s0 =
RF_W_wr=1
RF_s0=0
RF_Rp_zero
RF_W_addr=ra
RF_Rp_addr=ra
RF_Rq_add=rc
RF_Rq_addr=rc
Jump-if-
RF_W_wr=1
RF_Rp_rd=1
RF_Rq_rd=1
RF_Rq_rd=1
zero-jmp ?
RF_W_addr_ra
RF_W_addr=ra
PC_ld=1
RF_W_wr=1
RF_W_wr=1
alu_s1 =
alu_s1=1
RF_Rp_zero'
alu_s0 = 1
alu_s0=0
RF_Rp_zero

24. Program for the Six-Instruction Processor
First, the load constant instruction requires that the register file be able to load data from IR[7..0], in addition to data from data memory or the ALU output. Thus, we widen the register file’s multiplexer from 2x1 to 3x1, add another mux control signal, and also create a new signal coming from the controller labeled RF_W_data, which will connect with IR[7..0]—these changes are highlighted by the dashed circle labeled “1” in Figure Second, the subtract instruction requires that we use an ALU capable of subtraction, so we add another ALU control signal—highlighted by the dashed circle labeled “2” in the figure. Third, the jump-if-zero instruction requires that we be able to detect if a register is zero, and that we be able to add IR[7..0] to the PC. Thus, we insert a datapath component to detect if the register file’s Rp read port is all zeros (that component would just be a NOR gate), labeled as dashed-circle “3a” in the figure. We also upgrade the PC register so it can be loaded with PC plus IR[7..0], labeled as “3b” in the figure. The adder used for this also subtracts 1 from the sum, to compensate for the fact that the Fetch state already added 1 to the PC.
Program for the Six-Instruction Processor
Example program – Count number of non-zero words in D[4] and D[5]
Result will be either 0, 1, or 2
Put result in D[9] I
_rd
PC_ld
PC_clr
PC_inc
IR_ld

25. Further Extensions to the Programmable Processor
8.5
Further Extensions to the Programmable Processor
Typical processor instruction set will contain dozens of data movement (e.g., loads, stores), ALU (e.g., add, sub), and flow-of-control (e.g., jump) instructions
Extending the control-unit/datapath follows similarly to previously-shown extensions
Input/output extensions
Certain memory locations may actually be external pins
e.g, D[240] may represent 8-bit input I0, D[255] may represent 8-bit output P7
256 x
16 D
W_data
R_data
addr rd wr 0: 1: 2:
239:
240:
241:
248:
255:
00..0 I 1 P0 P7

26. Program using I/O Extensions – Recall Chpt 1 C-Program Example
Programmed
microprocessor
Custom designed
digital circuit
Desired motion-at-night detector
Microprocessors a common choice to implement a digital system
Easy to program
Cheap (as low as $1)
Available now M I P0
void main() {
while (1) {
P0 = I0 && !I1;
// F = a and !b, } 1 op r a o r I 1 P1 c I 2 P2 1 I 3 P3 b I 4 P4 I 5 P5 1 I 6 P6 F I 7 P7
6:00
7:05
7:06
9:00
9:01
time

27. Program Using Input/Output Extensions
Underlying assembly code for C expression I0 && !I1.
0: MOV R0, 240 // move D[240], which is the value at pin I0, into R0
1: MOV R1, 241 // move D[241], which is that value at pin I1, into R1
2: NOT R1, R1 // compute !I1, assuming existence of a complement instruction
3: AND R0, R0, R1 // compute I0 && !I1, assuming an AND instruction
4: MOV 248, R0 // move result to D[248], which is pin P0
256 x
16 D
W_data
R_data
addr rd wr 0: 1: 2:
239:
240:
241:
248:
255:
00..0 I 1 P0 P7
void main() {
while (1) {
P0 = I0 && !I1;
// F = a and !b, }

28. Chapter Summary Programmable processors are widely used
Easy availability, short design time
Basic architecture
Datapath with register file and ALU
Control unit with PC, IR, and controller
Memories for instructions and data
Control unit fetches, decodes, and executes
Three-instruction processor with machine-level programs
Extended to six instructions
Real processors have dozens or hundreds of instructions
Extended to access external pins
Modern processors are far more sophisticated
Instructive to see how one general circuit (programmable processor) can execute variety of behaviors just by programming 0s and 1s into an instruction memory