1. Low Power and High Speed Multi Threshold Voltage Interface CircuitsBy
Sherif A. Tawfik and Volkan Kursun
Presented by
Ramasamy Ethiraj

2. Contents Introduction Standard Feedback-Based Level Converters
Proposed Multi-Vth Level Converters
Delay and Power consumption of level Converters
- Comparison of level converters
- The performance of level converters under Supply Voltage
and Process Parameter Variations
- Multi Vth-CMOS Technology
CONCLUSION

3. Introduction Scaling the supply voltage to reduce the power
Lower supply will degrade the speed
Multi-VDD Techniques and Conventional Level converters are introduced.
Conventional Level converters will introduce DC current and feedback circuit (hence slow response)
Multi-Vth Level converters will eliminate DC current and Feedback circuit.

4. Standard Level Converters 1 (LC1)
VDDL is directly connected to M3 & M4 – DC path. So high power
Feedback circuit – more delay.
M1 & M2 should be large, because VDDL is directly connected. Result in large capacitance and area

5. Standard Level Converters 2 (LC2)
VDDL is not directly connected to PMOS – still some DC current
Feedback circuit – more delay.
More device count- more delay and power
M2 should be large, because VDDL is directly connected. Result in large capacitance and area

6. Proposed Multi-Vth Level Converter1 (PC1)
Vth-M2 should be more negative than VDDL –VDDH to avoid DC current
No feedback circuit – less delay.
less device count- less delay, area and power
Smaller transistor sizes.

7. Proposed Multi-Vth Level Converter2 (PC2)
Vth-M2 should be more negative than VDDL –VDDH to avoid DC current
Multi Vth is used for M3.
Lowest delay compare to other converters
No feedback circuit – less delay.
Smaller transistor sizes.

8. Proposed Multi-Vth Level Converter2 (PC2)
Vth-M2 should be more negative than VDDL –VDDH to avoid DC current
M3,M4,C is removed for lower VDDL
No feedback circuit – less delay.
Smaller transistor sizes.

9. Simulation Setup 0.18um technology VDDH = 1.8V
Simulated for different VDDL : 0.5, 1 and 1.2V
Wn = Wmin, Wp = 2.5Wn
Delay is measured between input of ID and Node2
Power consumption measured for entire setup

10. Optimum Delay and Power measurements

11. Normalized to LC2

12. The performance of level converters under Supply Voltage and Process Parameter Variations

13. Power and Delay comparison – LC2 vs
Power and Delay comparison – LC2 vs. PC2 for Power optimized circuit (VDDL = 1.2V)

14. Power and Delay comparison – LC2 vs
Power and Delay comparison – LC2 vs. PC1 for Power optimized circuit (VDDL = 1V)

15. Power and Delay comparison – LC2 vs
Power and Delay comparison – LC2 vs. PC1 for Power optimized circuit (VDDL = 0.5V)

16. Vth-M2 vs. Power and Delay

17. Conclusions
• Multi-Vth level converters has up to 78% less delay compare to standard level converters
70% less power consumption
Less Device count and size – minimum Area
Wide range of threshold voltages
High speed and low power.

18. Thank You