1. ADITI SHINDE CHIDAMBARAM ALAGAPPAN
CPU DESIGN PROJECT
ADITI SHINDE
CHIDAMBARAM ALAGAPPAN

2. Features Multicycle Datapath 16 Registers
16 instructions having 4 bit opcode

3. ISA R -TYPE: I TYPE J-TYPE B-TYPE Opcode (4) Src 1 (4) Src 2(4)
Dest (4)
Opcode
Src (4)
Dest(4)
Imm val.
Opcode (4)
Jump Address (12)
Opcode(4)
Reg1
Reg2
Label

4. REGISTERS NAME FUNCTION NUMBER $zero Hard wired zero $0 $at
Used for pseudo-instructions $1
$ra
Return address $2
$s0-$s3
Saved registers
$3-$6
$to-$t3
Temporary registers
$7-$10
$a0 and $a2
Arguments registers
$11-$12
$v0-$v2
Value registers
$12-$15

5. Multicycle Datapath Memory ALU Instr. reg. (IR) PC A Register file
PCS
PCW
12 to 15 to
Control
FSM
0-11 RW
8-11
4-7 PC
Instr. reg. (IR) A
Addr.
Memory
0-3
Register file
ALU
ALUA
ALUB
AOut ID
Data
Mem. Data Reg (MDR) B RD
IRW 1
Control
unit
Sign
extend
MRg -1 MW
12-15

6. FSM Start State 0 1 Instr. fetch/ adv. PC lw or sw J R B 3 2 Read
decode/reg.
fetch/branch
addr.
lw or sw J R B 3 2
Read
memory
data
Compute
memory
addr.
ALU
operation
Write
jump addr.
to PC
Write PC
on branch
condition lw 6 8 9 sw 4 5
Write
register
Write
memory
data 7
Write
register

7. INSTRUCTION SET
1. Add 2. Sub 3. And 4. Or 5. Nor 6. Slt 7. Lw 8. Sw 9. Addi 10. Andi 11. Beq 12. Jump 13. Jal 14. Jr

8. PROBLEMS FACED Smaller value of offset (4 bits) Halt – Hardwired -1
Opcode (4)
Src (4)
Imm.val

9. PROSPECTIVE CHANGES Micro programmed Control Unit
Hardware changes for faster execution
Effective programming for preventing latches
Reduce critical path delay for accommodating faster execution

10. QUESTIONS ??