1. BIC 10503: COMPUTER ARCHITECTURE
Chapter 4 Input Output

2. Overview 4.1 External Device 4.2 I/O Module 4.3 Programmed I/O
4.4 Interrupt-Driven I/O
4.5 Direct Memory Access (DMA)
4.6 I/O Channel and Processor

3. 4.1 External Device

4. External Devices
Provide a means of exchanging data between the external environment and the computer
Attach to the computer by a link to an I/O module
The link is used to exchange control, status, and data between the I/O module and the external device

5. External Devices (cont.)
Three categories :-
Human readable
interface to user
Screen, printer, keyboard
Machine readable
Interface to equipment
Monitoring and control
Communication
Interface to remote devices
Modem
Network Interface Card (NIC)

6. Generic Model of an I/O Module

7. Keyboard / Monitor Most common means of computer/user interaction
User provides input through the keyboard
The monitor displays data provided by the computer
Basic unit of exchange is the character
IRA (International Reference Alphabet)
Characters are represented by Codes (7/8 bits length)
2 types : printable, non- printable
Keyboard / Monitor

8. External Device Block Diagram
Control Signal
What is the device function?
READ / WRITE ?
Data Bits
Actual data to be sent / received
Status Signals
Device state
READY / NOT-READY

9. Input/Output Problems
Wide variety of peripherals (devices)
Delivering different amounts of data – data length transferred to network adapter is not same with hard disk
At different speeds – printer is much slower than CD-ROM
In different formats - .wav, .bmp etc
All slower than CPU and RAM
Solution - Need I/O modules/controller

10. 4.2 I/O Module
Interface to CPU and Memory
Interface to one or more peripherals

11. I/O Module Functions Control and timing Processor communication
- to coordinate the flow of traffic between internal resources and external devices
Processor communication
- I/O module must communicate with the processor and with the external device
Device communication
- This communication involves commands, status information, and data
Data buffering
- The data are buffered in the I/O module and then sent to the peripheral device at its data rate
Error detection
- Some form of error-detecting code is often used to detect transmission errors

12. I/O Module Structure

13. I/O Steps
CPU checks I/O module device status
I/O module returns status
If ready, CPU requests data transfer
I/O module gets data from device
Data being transferred between I/O module and CPU

14. I/O Module Capabilities
Hide or reveal device properties to CPU
Support multiple or single device
Control device functions
Also O/S decisions
e.g. Unix treats everything it can access/control as a file

15. Direct Memory Access (DMA)
I/O Techniques
3 techniques are possible for I/O Operations to read data from a device to memory :-
Programmed I/O
— CPU controls the entire process
— Can waste CPU time
Interrupt-driven I/O
— CPU issues command
— Device proceeds and leaves CPU free
Direct Memory Access (DMA)
— Device exchanges data directly with memory

16. Table 7.1 I/O Techniques

17. 4.3 Programmed I/O

18. CPU has direct control over I/O
Programmed I/O
CPU has direct control over I/O
— Sensing status
— Read/write commands
— Transferring data
CPU waits for I/O module to complete operation
CPU has to wait the current operation/command to finish, which degraded the entire system performance
Wastes CPU time

19. Programmed I/O – Flowchart to read a Block of Data

20. Programmed I/O - detail
CPU requests I/O operation
I/O module performs operation
I/O module sets status (complete/not-complete)
I/O module does not inform CPU directly
CPU checks status bits periodically
I/O module does not interrupt CPU
CPU may wait or come back later

21. I/O Commands
There are four types of I/O commands that an I/O module may receive when it is addressed by a processor:
Control
- used to activate a peripheral and tell it what to do
Test
- used to test various status conditions associated with an I/O module and its peripherals
Read
- causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer
Write
- causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral

22. Addressing I/O Devices
Under programmed I/O data transfer is very like memory access (CPU viewpoint)
Each device given unique identifier
CPU commands contain identifier (address) of the device

23. I/O Address Mapping Memory mapped I/O Isolated I/O
Single address space for memory location and I/O devices (shared address space)
I/O looks just like memory read/write
No special commands for I/O
Large selection of memory access commands available
Isolated I/O
Separate address spaces for memory location and I/O devices
Need I/O or memory select lines
Special commands for I/O
Limited set

24. }
Memory
Mapped
I/O }
Isolated
I/O

25. 4.4 Interrupt-Driven I/O

26. Interrupt-Driven I/O
The problem with programmed I/O is that the processor has to wait a long time for the I/O module to be ready for either reception or transmission of data
An alternative is for the processor to issue an I/O command to a module and then go on to do some other useful work
The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor
The processor executes the data transfer and resumes its former processing

27. Interrupt-Driven I/O
Overcomes CPU waiting
Avoids repeated checking of device by CPU (polling)
I/O module interrupts when ready

28. Interrupt-driven I/O – Flowchart to read a Block of Data

29. Two design issues arise in implementing interrupt I/O:
Because there will be multiple I/O modules how does the processor determine which device issued the interrupt?
If multiple interrupts have occurred how does the processor decide which one to process?

30. Design Issues – Possible Solutions
using Device Identification mechanisms :-
Multiple Interrupt Lines
Different line for each module
But cannot utilize so much bus or cpu pins to interrupt lines
However, lines can be shared between devices, and these will use one of the following techniques
Software poll
When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll each I/O module to determine which module caused the interrupt
Time consuming

31. Design Issues – 4 Possible Solutions
Daisy Chain or Hardware poll
The interrupt acknowledge line is daisy chained through the modules
Vector – address of the I/O module or some other unique identifier
Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine, avoiding the need to execute a general interrupt-service routine first
Bus Arbitration
An I/O module must first gain control of the bus before it can raise the interrupt request line
When the processor detects the interrupt it responds on the interrupt acknowledge line
Then the requesting module places its vector on the data lines

32. Drawbacks of Programmed and Interrupt-Driven I/O
Both forms of I/O suffer from two inherent drawbacks:
The I/O transfer rate is limited by the speed with which the processor can test and service a device
The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer
When large volumes of data are to be moved a more efficient technique is direct memory access (DMA)

33. 4.5 Direct Memory Access (DMA)

34. DMA – Flowchart to read a Block of Data
CPU sends read commands to DMA module.
DMA module transfers the entire block of data, directly to memory.
When transfer completed, DMA module sends interrupt signal to CPU.

35. Interrupt driven and programmed I/O require active CPU intervention
DMA
Interrupt driven and programmed I/O require active CPU intervention
Transfer rate is limited (by the speed and size)
CPU is tied up – a lot of instructions need to be processed
When involved a large volume of data/instructions
DMA allows devices to communicate directly with memory without passing data through the CPU

36. Typical DMA Block Diagram
When the processor wishes to read or write a block of data, it will send the following information to DMA module:
READ/WRITE - Using the read/write control line between the processor and the DMA module
ADDRESS - The address of the I/O device involved, communicated on the data lines
START LOCATION - The starting location in memory to read/write, communicated on the data lines and stored by the DMA module in its address register
WORD COUNT - The number of words to be read/written, communicated via the data lines and stored in the data count register

37. Various DMA Configurations

38. 4.6 I/O Channel and Processor

39. Evolution of the I/O Function
The CPU directly controls a peripheral device.
A controller or I/O module is added. The CPU uses programmed I/O without interrupts.
Same configuration as in step 2 is used, but now interrupts are employed. The CPU need not spend time waiting for an I/O operation to be performed, thus increasing efficiency.
The I/O module is given direct access to memory via DMA. It can now move a block of data to or from memory without involving the CPU, except at the beginning and end of the transfer.
The I/O module is enhanced to become a processor in its own right, with a specialized instruction set tailored for I/O
The I/O module has a local memory of its own and is, in fact, a computer in its own right. With this architecture a large set of I/O devices can be controlled with minimal CPU involvement.

40. I/O Channels
I/O devices getting more sophisticated
e.g. 3D graphics cards
CPU instructs I/O controller to do transfer
I/O controller does the entire transfer to device, which is instructed by I/O Channels
I/O channels are components that has the ability to execute instructions
2 types of I/O channels
selector channel
select one device at a time
multiplexor channel
select multiple device

41. I/O Channel Architecture - 2 types
Selector
I/O Channel Architecture - 2 types
Multiplexor

42. Interfacing
Connecting peripheral/device to an I/O module
2 types of interfacing:
- serial – 1 line to transmit data
- parallel – multiple lines
Traditional usage - parallel for high speed, serial for low speed

43. Interfacing (cont.)
Recent develop in high-speed serial interfaces have given serial devices the advantage. Eg:
USB
Gigabit ethernet
SATA drives
Why? Because :
Serial cables are smaller and easier to manage electrically
Interference between lines limits speed of parallel interfaces
Synchronization of lines poses a problem at high speed and limits cable length
Parallel cables are bulky and require lots of shielding

44. Parallel and Serial I/O

45. Thank You