1. Dhiraj Parashar Shiva Prasad Behera Vivek Sharma
RISC vs. CISC
Dhiraj Parashar
Shiva Prasad Behera
Vivek Sharma
11/9/2018
CS654

2. Overview Introduction Key arguments Comparisons Post-RISC
Current Trends
I’ll begin this presentation by given an introduction of the risc/cisc. We will try to reason out what factors led to evolution of risc and cisc, and what effects these archi’s have on the system development.
11/9/2018
CS654

3. CISC Evolution Storage and Memory Support for high-level languages
High cost of memory.
Need for compact code.
Support for high-level languages
Ease of adding new microinstructions
Marketing Strategy
Compilers were at very early state of development then.
To sell there product the marketing people needed to show that there product is more complex and therefore has a better performance.
11/9/2018
CS654

4. CISC Effects Moved complexity from s/w to h/w Compact code
Ease of compiler design (HLLCA)
Easier to debug
Lengthened design times
Increased design errors
Close the semantic gap between hll and machine code
As pointed out in one of the papers the microinsruction code became so complex that several patches had to applied after the release.
11/9/2018
CS654

5. RISC Evolution Increasingly cheap memory
Improvement in compiler technology
Patterson: “Make the common case fast”
More complex instructions never used by compilers. These rarely used instructions could be eliminated without any loss in performance. We are directly executing the instructions…no microprogramming. Uniform instruction format
IBM example 48 represents of all the instr. executed out of 183 for a cobol compiler.
11/9/2018
CS654

6. RISC Effect Move complexity from h/w to s/w
Provided a single-chip solution
Better use of chip area
Better Speed
Feasibility of pipelining
Single cycle execution stages
Uniform Instruction Format
As microinstruction h/w is thrown out we can add more registers and caches for improved performance.
11/9/2018
CS654

7. Key arguments RISC argument CISC argument
for a given technology, RISC implementation will be faster
current VLSI technology enables single-chip RISC
when technology enables single-chip CISC, RISC will be pipelined
when technology enables pipelined CISC, RISC will have caches
CISC argument
CISC flaws not fundamental (fixed with more transistors)
Moore’s Law will narrow the RISC/CISC gap (true)
software costs will dominate (very true)
11/9/2018
CS654

8. Role of Compiler:RISC vs. CISC
CISC instruction:
MUL <addr1>, <addr2>
RISC instructions:
LOAD A, <addr1>
LOAD B, <addr2>
MUL A, B
STORE <addr1>
RISC is dependent on optimizing compilers
1). Load delay slot.
2) Advantage of non-blocking cache in case of a cache miss.
11/9/2018
CS654

9. Comparisons The Case for RISC (1980) Colwell et al. (1985)
Introductory paper advocating RISC
Colwell et al. (1985)
Comparison studies misleading
Envisions use of techniques from both
Clark, Bhandarkar (1990)
MIPS M/2000 vs. VAX 8700
Unfair comparison (?!)
11/9/2018
CS654

10. Post-RISC Architecture
Additional functional units for superscalar
Additional “non-RISC” (but fast) instructions
Increased pipeline depth
Branch prediction
Out of order execution
11/9/2018
CS654

11. Current Trends
P6 - x86 instructions decoded into RISC-like instructions (ROps)
Intel called this hack CRISC. This concept was so moronic that even Intel could not market it!
IA-64 - dependence on compilers for scheduling
Athlon – both direct execution and micro-programmed instructions
11/9/2018
CS654

12. Thanks!
11/9/2018
CS654