1. Data Hazards and Stalls
Data hazards and forwarding
Data Hazards and Stalls
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2. An Example
Assuming that register R2 = 10 initially. And the sub instruction will result in R2 = -20.
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3. Note: only add and sw get the right value R2 = - 20
See P&H Fig rd Ed or th Ed
Pipelined dependencies in a five instruction sequence using simplified datapaths to show the dependencies.
Note: only add and sw get the right value R2 = - 20
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4. An Example (cont’d)
Hazard condition (between sub and and at the indicated stages):
EX/MEM.RegisterRd = ID/EX.RegisterRs = $2
General
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Question: can you identify which of the 4 conditions here captures the hazards condition between sub and or ?
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5. Forwarding/Bypassing
ALU inputs can also from pipeline registers.
Extra multiplexors.
Hazard detection units.
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6. See P&H Fig rd Ed or th Ed
The dependencies between the pipeline registers move forward in time, so it is possible to supply the inputs to the ALU needed by the and instruction and or instruction by forwarding the results found in the pipeline registers rather than stall.
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7. The ALU and pipeline register before adding forwarding.
See P&H Fig rd Ed or th Ed
The ALU and pipeline register before adding forwarding.
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8. Forwarding control and the multiplexors are added
See P&H Fig rd Ed or th Ed
Forwarding control and the multiplexors are added
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9. The control values for the forwarding multiplexors.
See P&H Fig rd Ed or th Ed
The control values for the forwarding multiplexors.
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10. Forwarding Conditions
1. EX hazard:
if(EX/MEM.RegWrite
and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10
if (EX/MEM.RegWrite
and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10
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11. and (MEM/WB.RegisterRd ≠ 0)
Con’d
2. MEM hazard:
if(MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01
and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01
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12. Priority in Forwarding
Add $1, $1, $2
Add $1, $1, $3
Add $1, $1, $4 ….
Note: Here both EX and MEM stages may have the exact hazard conditions. What should we do ?
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13. Priority in Forwarding
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 0)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs) )
and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01
and (EX/MEM.RegisterRd = ID/EX.RegisterRt) )
and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01
Note: When both EX and MEM stages may have the exact hazard conditions.
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14. The datapath modified to resolve hazards via forwarding.
See P&H Fig rd Ed or th Ed
The datapath modified to resolve hazards via forwarding.
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15. The Snapshots of Our Example Through Forwarding
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16. Some conventions The bold lines are those active in a clock cycle.
The italicized register numbers in color with a red circle indicate a hazard.
The forwarding unit is highlighted by shading it when it is forwarding data to the ALU.
The … in the place of operands means that their identity is information not needed by the stage.
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17. Clock cycles 3 of the instruction sequence.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 3 of the instruction sequence.
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18. Clock cycles 4 of the instruction sequence.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 4 of the instruction sequence.
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19. Clock cycles 5 of the instruction sequence.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 5 of the instruction sequence.
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20. Clock cycles 6 of the instruction sequence.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 6 of the instruction sequence.
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21. Hazards and Stalls
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22. A pipelined sequence of instructions.
See P&H Fig rd Ed or th Ed
A pipelined sequence of instructions.
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23. The way stalls are really inserted into the pipeline
Bubble
The way stalls are really inserted into the pipeline
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24. The way stalls are really inserted into the pipeline
See P&H Fig rd Ed or th Ed
The way stalls are really inserted into the pipeline
(Another View)
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25. Forwarding with Load and Stores
The problem
The solution
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26. A Hazard Detection Unit
In the ID stage, the following should be checked by the hazard detection unit, so it can insert the stall between a load and its use.
if (ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
stall the pipeline
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27. Pipelined control overview, showing the two multiplexors for forwarding, the hazard detection unit, and the forwarding unit.
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28. Snapshots of the running example through the pipeline
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29. Clock cycles 2 of the instruction sequence in the example.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 2 of the instruction sequence in the example.
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30. Clock cycles 3 of the instruction sequence in the example.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 3 of the instruction sequence in the example.
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31. Clock cycles 4 of the instruction sequence in the example.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 4 of the instruction sequence in the example.
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32. Clock cycles 5 of the instruction sequence in the example.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 5 of the instruction sequence in the example.
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33. Clock cycles 6 of the instruction sequence in the example.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 6 of the instruction sequence in the example.
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34. Clock cycles 7 of the instruction sequence in the example.
See P&H Fig rd Ed CD (For more practice section)
Clock cycles 7 of the instruction sequence in the example.
(note the forwarding of $4)
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35. Branch Hazards and Handling
Branch hazard handling methods
Static
Dynamic
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