1. CS/COE0447 Computer Organization & Assembly Language
Chapter 5 Part 3
Short reference version

2. Multi-Cycle Execution: R-type
Instruction fetch
IR <= Memory[PC]; sub $t0,$t1,$t2
PC <= PC + 4;
Decode instruction/register read
A <= Reg[IR[25:21]]; rs
B <= Reg[IR[20:16]]; rt
ALUOut <= PC + (sign-extend(IR[15:0])<<2);
Execution
ALUOut <= A op B; op = add, sub, and, or,…
Completion
Reg[IR[15:11]] <= ALUOut; $t0 <= ALU result

3. Multi-cycle Execution: lw
Instruction fetch
IR <= Memory[PC]; lw $t0,-12($t1)
PC <= PC + 4;
Instruction Decode/register read
A <= Reg[IR[25:21]]; rs
B <= Reg[IR[20:16]];
ALUOut <= PC + (sign-extend(IR[15:0])<<2);
Execution
ALUOut <= A + sign-extend(IR[15:0]); $t (sign extended)
Memory Access
MDR <= Memory[ALUOut]; M[$t ]
Write-back
Load: Reg[IR[20:16]] <= MDR; $t0 <= M[$t ]

4. Multi-cycle Execution: sw
Instruction fetch
IR <= Memory[PC]; sw $t0,-12($t1)
PC <= PC + 4;
Decode/register read
A <= Reg[IR[25:21]]; rs
B <= Reg[IR[20:16]]; rt
ALUOut <= PC + (sign-extend(IR[15:0])<<2);
Execution
ALUOut <= A + sign-extend(IR[15:0]); $t (sign extended)
Memory Access
Memory[ALUOut] <= B; M[$t ] <= $t0

5. Multi-cycle execution: beq
Instruction fetch
IR <= Memory[PC]; beq $t0,$t1,label
PC <= PC + 4;
Decode/register read
A <= Reg[IR[25:21]]; rs
B <= Reg[IR[20:16]]; rt
ALUOut <= PC + (sign-extend(IR[15:0])<<2);
Execution
if (A == B) then PC <= ALUOut;
if $t0 == $t1 perform branch

6. Multi-cycle execution: j
Instruction fetch
IR <= Memory[PC]; j label
PC <= PC + 4;
Decode/register read
A <= Reg[IR[25:21]];
B <= Reg[IR[20:16]];
ALUOut <= PC + (sign-extend(IR[15:0])<<2);
Execution
PC <= {PC[31:28],IR[25:0],”00”};

7. Fig 5.28 Our final multicycle datapath

8. A FSM State Diagram