1. 10-Nov-18
ESD Protection Design Seminar Jim Sutherland Senior Applications Engineer
INTRODUCTION - Slide 1 A

2. Outline What is ESD? What damage can it cause?
10-Nov-18
What is ESD?
What damage can it cause?
Why is the problem growing?
What are the issues for the designer?
How can we measure it?
How can we protect equipment from ESD?
Outline - Slide 2
This talk will answer these questions with most of the time spent on the last two topics.

3. What Is ESD? ESD = Electro Static Discharge Generation Discharge
10-Nov-18
ESD = Electro Static Discharge
Generation
Triboelectric (friction causes accumulation of charge)
Induction (field induces charge)
Discharge
Dielectric (air) breakdown
Electric field increases when charged bodies approach each other
Current flow into circuitry
WHAT IS ESD? - Slide 3
ESD is an uncontrolled discharge of electricity in a normal environment that can damage electronic equipment, e.g. a person walking across a synthetic fiber carpet and touching a laptop computer connector pin can damage it.
GENERATION: ES charges are typically generated by frictional contact between two insulators that can transport charged particles from one to the other. The charges stay statically on the surface and do not flow away as they would on a conductor (through a path to ground). Tribo = rub in Greek. There is a Tribo-Electric Series list that is an ordering of materials by their ability to accumulate either a positive or negative charge. ES charges can also be generated by other methods such as induction (bringing a charged object close to another object).
DISCHARGE: Charged objects have associated with them an electric field. When brought closer together the field strength increases to a point where the medium between the two (air typically) becomes conductive, causing a dielectric breakdown, known as an ESD event. If the discharge “spark” contacts a conductor on electronic circuitry, current will flow in the circuit. The breakdown of air is about 30kV/cm.

4. What Damage Does ESD Cause in ICs? - Slide 4
10-Nov-18
ESD Damage of ICs
Permanent
Oxide breakdown, shorts, opens, latch-up
Temporary
Latch-up, ground bounce
Latent
Degradation from an ESD event
What Damage Does ESD Cause in ICs? - Slide 4
Permanent damage is caused when the ESD voltage & current on the CMOS oxide is so high that punch-through breakdown occurs.
Temporary “latch-up” damage occurs when an input overvoltage causes a parasitic Silicon Controlled Rectifier to be created in the IC that causes a heavy current flow from VCC to GND and causes the IC to stop working. If the current flow is too large and too long, permanent damage can result, if not, the circuit will operate normally if it is given a power reset. A large ESD current flowing in a PCB ground trace that has high inductance can cause “ground bounce” which can cause data drop-outs or latch-up.
Latent damage results when the circuitry is degraded when an ESD event occurs, but not enough to cause an immediate failure.

5. WHY IS THE ESD PROBLEM GROWING? - Slide 5
10-Nov-18
ESD problem is growing
Circuits/Systems
Old - Robust ICs & Low speed signals
New - Sensitive ICs & High speed signals
Environment
Old - Manufacturing / Corporate
New - Home / Outdoors / Person
WHY IS THE ESD PROBLEM GROWING? - Slide 5
Circuits & Systems used to be comprised of large geometry Bipolar & CMOS ICs that had thick gate oxides and ran low speed signals at 5 volt levels. Now we have virtually all CMOS circuits with thin gate oxides running at 3 volts and more susceptible to damage from lower levels of energy from undesirable sources. We are also operating systems at such high frequencies, that the low pass filters we used to add to eliminate ESD pulses, are starting to filter out the desired signals.
Years ago the main handlers of ICs were the IC manufacturers and maintenance technicians for the mainframe and personal computers in a corporate environment. Now, electronic devices are being used more directly by many more non-corporate users, who have more direct access to the circuitry, and in more uncontrolled environments, e.g. A laptop computer that is used in a home or hotel room where the user plugs in a modem card after walking across a very non-conductive carpet, or a cell phone user in his tent in the desert who plugs a FAX machine into his phone.
Department Of Defense DOD Study quoted in 1989 article says 50% of all IC field failures are due to ESD (from book by Buchanan 1996). Another article said 8 to 33% of IC failures are due to ESD.

6. ESD Issues for the Designer
10-Nov-18
ESD Issues for the Designer
Must meet ESD specifications
Select ESD tolerant components
Minimize signal degradation (from R,L & C)
Board space / weight / proper design
Component cost
Assembly cost
Lifetime cost (stability)
Test the system
ESD ISSUES FOR THE DESIGNER - Slide 6
Increasingly, ESD performance levels have become part of system specifications, e.g. all European countries now require ESD protection. The designer will have the task of figuring out on how to meet these specifications.
This entails selecting the right components. He must be careful in adding resistors, inductors or capacitors so that his chosen solution does not lead to unacceptable levels of signals degradation. He must be concerned about available board space limits and in the case of portable equipment, about exceeding weight limits.
He needs to be concerned about the cost of his solution and that means not only the cost of components but the manufacturing, inventory, and life-time (reliability) costs as well. And finally he needs to test the design for compliance with ESD standards.

7. International ESD Standards
10-Nov-18
International ESD Standards
Human Body Model (HBM) - for devices
EIA/JESD22-A114-A
ANSI/EOS/ESD-S
MIL-STD-883 (method 3015)
IEC : for systems
Machine Model (MM) - less common
EIA/JESD22-A115-A
Charge Device Model (CDM) - less common
JESD22-c101
INTERNATIONAL ESD STANDARDS - Slide
‘If you can not measure it, you are not being scientific’. So a number of ESD models attempt to simulate the nature of an ESD event in the controlled environment of a laboratory. We are listing 4 standards here. The Human Body Model and the IEC 1000 are the more important ones for us and we will look at them in more detail.
The Human Body Model seeks to emulate human touch and was originally described in Method 3015 of MIL-STD-883. It has been formalized by both a JEDEC spec and one generated by the ANSI and ESD Associations. It is a specification for devices.
The IEC Specification is a relatively new spec that has come from the European Union and is finding rapid acceptance as a specification for systems.
The last two models are intended to model manufacturing environments. The Machine Model found acceptance in Japan in the early 70s. This model represents the manufacturing environment of automated assembly machines which have higher capacitances than the human body. It uses lower voltages and higher currents (there is no current limiting resistor in this model) which make it a more severe test then the others.
Finally, the Charged Device Model may be used in conjunction with other models. It is intended to model the case where the component itself acquires the charge that is later discharged when it contacts a metallic surface which is typical in the rails of an IC handler.

8. 10-Nov-18
Human Body Model (HBM)
Discharge from 100pF capacitor through 1.5 kOhm resistor
6 ESD pulses
3 positive, 3 negative
> 1 sec separation
Pin-to-pin testing
N(N-1)/2 combinations
Used for component characterization
Widely used
HUMAN BODY MODEL - Slide
This slide shows the basic configuration of the HBM. It is a 100 pF capacitor and a 1500 Ohm series resistor. The capacitor can be charged positive or negative with respect to reference terminal B. Once charged and the switch closes, the Device Under Test is exposed to the ESD event.
Six pulses are required, three positive and three negative with at least one second of separation between pulses.
The Standard defines Pin to Pin testing and so for a device with N pins there are approximately N(N-1)/2 possible combinations.
The Human Body Model is used for component testing and is therefore typically used on devices in Integrated Circuit packages.
It is one of the most widely used standards

9. HBM Current Waveform Rise Time: 2 nS < Tr <10 nS
10-Nov-18
HBM Current Waveform
HBM CURRENT WAVEFORM - Slide
This is the current waveform for the Human Body Model as measured through a short circuit. Remember however that there is a 1500 Ohm current limiting resistor in this model. Rise time is typically less than 10 nS and the pulse duration is less than 500 nS. If the ESD voltage were 4kv the current would be 2.5A (4000v  1500 Ohms = 2.5A).
Rise Time: 2 nS < Tr <10 nS

10. 10-Nov-18
IEC :1995 Standard
Discharge from 150 pF capacitor through 330 ohm resistor
6 ESD pulses
3 positive, 3 negative
Used for system characterization
“Contact” v. “Air” discharge
Different levels
Different applications
IEC : 1995 STANDARD - Slide
Notice that the model is very similar to the Human Body Model. However there are some important differences. The capacitor here is 150 pF so there is more energy in the ESD event but more importantly, the current limiting resistor is only 330 Ohm. That means that for the same ESD voltage, the peak currents for IEC 1000 are almost 5X higher than those for the HBM.
Here again six pulses, three positive and three negative with at least one second of time between discharges are required.
Note that IEC1000 is a system specification and not a specification for device testing.
Finally, this specification defines both ‘air’ discharges and ‘contact’ discharges. These two are for different applications and have different ESD levels as we will see later.

11. IEC 1000-4-2 Current Waveform
10-Nov-18
IEC Current Waveform
60ns
IEC CURRENT WAVE FORM - Slide
Two things should be noted here. First, the rise time to the peak current is less than 1nS and second, the ESD pulse is pretty much finished in under 80 nS. It should be obvious that with such rise times board layouts for protecting components become extremely critical. Now let’s take a look at the different voltage test levels mentioned earlier.
Very fast rise time: Tr < 1nS

12. 10-Nov-18
IEC Test Levels
Contact discharge is the preferred test method air discharges are not repeatable
Air discharges used where contact discharge cannot be applied
No implied equivalence in test severity between the two test methods
IEC TEST LEVELS - Slide
The IEC1000 defines four standard test levels and allows for some unique level in the ‘Special’ row of this table. Contact discharge varies from 2 to 8 kV whereas air discharge go up to 15kV. Contact discharge remains the preferred test methods since repeatability is a problem for air discharges. Air discharges are only used if contact discharges are not practical. Although the two are shown side by side in the table there is no implied equivalence in test severity between the two.

13. IEC 1000-4-2 Bench Test Specification
10-Nov-18
IEC BENCH TEST SPECIFICATION - Slide
The specification is quite complete and includes a detailed description of the Test setup required to do the actual measurements. A copper or aluminum ground plane is required to act as a Ground Reference Plane (GRP).
The Equipment Under Test is hooked up to the power source as required for operation under normal conditions and stands on a wooden table. Note that the return of the ESD probe and the ground of the power system are connected to the Ground Reference Plane.
Horizontal and vertical coupling planes, when specified, must be of the same material as the GRP and must be connected to the GRP with cables having 470k Ohm resistors at both ends.

14. ESD Protection Techniques
10-Nov-18
Clamp diodes in IC
Not sufficient protection
Shielding
Low effectiveness
Bypass capacitor or series resistor/inductor
Can degrade signal; many components; large board area
Spark gap
Low cost; low stability; large board area
Discrete Zener diodes
High capacitance, many components; large board area
Discrete PN diodes
Low capacitance; many components; large board area
Integrated PN diodes
ESD PROTECTION TECHNIQUES - Slide
Clamp diodes in IC This only provides 1-2kv protection, which is not sufficient for most applications
Shielding It is rare that radiated ESD has enough field energy to couple into a wire to cause damage, but it can cause a data loss. Protection from radiated ESD can be obtained with shielding, and any of the following methods.)
Obvious protection methods are the use of signal bypass capacitors, or series resistors or inductors (especially ferrite beads) . However, these will degrade signal transitions and but used with caution. They may also requires a fair amount of board space and raise the component count.
Another possibility is the Spark Gap. Typically, some interdigitated structure on a PCB connected between the signal and the power line. They are typically low cost but consume board space and have very poor repeatability and reliability. A carbon film form during breakdown that builds up to be a resistor.
Discrete Zener diodes can be used. However, since the current flows in the breakdown direction the larger Avalanche diodes must be made quite husky, and therefore tend to have relatively large diode capacitances (about 100pF) that can degrade high frequency signals.
Discrete PN diodes can used effectively as ESD protectors. Their capacitance can be made much lower than the Zener because the current conduction is in the forward direction (C might be only 5pF) so they won't filter out high frequency signals. They can handle high peak currents. Their disadvantage is a high component count and possibly more board space.

15. Integrated Diode Networks
10-Nov-18
Integrated Diode Networks
Superior downstream ESD protection
High speed response
ESD current steered to GND or VCC
Minimum Signal Degradation (Low C)
Minimal board space, weight
Low assembly/manufacturing costs
Minimal Design-In Time
Long-term reliability
INTEGRATED ESD DIODE NETWORKS - Slide
That brings us to what for many applications may be the best solution: the use of integrated diode networks. These diodes can be made fast so that they can effectively steer the ESD pulse to either Ground or Vcc, depending on its polarity.
They can be made with very low diode capacitance for minimal signal degradation.
They use little board space and minimize additional weight to portable systems.
They have lower assembly cost than discretes
PCB design-in time is minimal
Since they are semiconductors, they have excellent long term reliability.

16. Choosing an ESD Diode Network
10-Nov-18
How many lines are needed?
How much capacitance? (e.g. < 5 pF)
What is the HBM rating? (e.g. ±15 kV)
What is the downstream clamp voltage? (e.g kV HBM pulse)
What is the contact discharge rating? (e.g. ±8 kV)
What is the air discharge rating? (e.g. ±15 kV)
What package? (e.g. 24-pin QSOP)
CHOOSING AN ESD DIODE NETWORK - Slide
There are a number of questions the designer has to answer to determine the proper ESD protection scheme for his system. The answers I have provided in this situation point to specs of an ESD diode network protection device that we make at CMD.
. How many lines do I need to protect?
. How much additional capacitance can I tolerate on these lines?
. What ESD rating is needed for the protection of the downstream components?
. What system protection level am I trying to provide?
. What downstream clamp voltage can I tolerate?
. How large or how small a package do I need in this assembly?

17. ESD Diode Network Placement
10-Nov-18
ESD Diode Network Placement
The Need to Keep ESD Diodes
Downstream of Line Inductances
Preferred Layout
ESD Entry
Point
Parasitic L
Vcc
Gnd
Protected
Device
Poor layout - increased clamp voltage
due to parasitic inductance
ESD DIODE NETWORK PLACEMENT - Slide
Given the nature of ESD signals it is extremely important to pay attention to the actual placement of components on the board. With a typical rise time of 700 pS it does not take a lot of trace inductance on a board to make the ESD I transient pulse current effectively bypass the protection diodes and dump its energy in the device to be protected. The large amount of ESD current that flows through the Parasitic inductance means that it will have a large voltage drop across it, and that voltage drop will add to the diode drop, so the clamping voltage gets further away from the power supply voltage.
If we are dealing with signals that rise to 30 Amps of current in less than one nanosecond, it follows that for every nanoHenry of inductance, the voltage at the input of the device to be protected rises by 30 volts. Remember that the voltage at this input is equal to the Clamp voltage of the diodes plus the voltage across the inductor plus the supply voltage. So, if you have much parasitic inductance (10nH) in this path the input voltage can rise to 300 volts. (V = L (di/dt) = 10x10-9 H (30 A / S) = 300 V) The forward drop of the diode is typically well under 30v at the same 30A peak current so the voltage at the protected device is going to be dominated by the voltage across the parasitic L.
A much better situation is created when the protection diodes and the device to be protected are as close together as possible. In this case the parasitic series inductance actual helps reduce the ESD peak current and the protection diodes will work as intended.
Remember Z = L = 2fL , so the higher the frequency, the higher the impedance.
We don't know where the ESD will hit. So the above suggestion is the best protection no matter where the ESD strikes, especially while handling a PCB. If the ISD is most likely to enter through a connector, you might also put protective diodes near the connector.
Also put protection diodes at most likely ESD entry point - the connector

18. Designing for Minimal Power Rail Inductance
10-Nov-18
Designing for Minimal Power Rail Inductance
DESIGNING FOR MINIMAL POWER RAIL INDUCTANCE -Slide
A similar situation exists if there is inductance in the power rail. If you recall that we are dealing with signals that rise to 30 or 40 Amps of current in less than one nanosecond, it follows that for every nanoHenry of inductance the voltage at the input of the device to be protected rises by volts. Remember that the voltage at this input is equal to the Clamp voltage of the diodes plus the voltage across the inductor plus the supply voltage. So, if you have some inductance in this path the input voltage can easily rise to 100 to 200 volts.
V = L (di/dt) = 10exp-9 H (30 A / 10exp-9 S) = 30 V
So, since the inductance impedes transient (fast transition) current flow. put the ESD Diode Network next to the device to be protected, so the ESD current prefers to go on a low impedance path to the power supply, and not to the device-to-be-protected.
Keep inductance low. Use ground planes for Vcc & Ground. Keep connections short and wide.

19. 10-Nov-18
Add Bypass Capacitor
Vcc
Protected
Device C
Gnd
Place Ceramic bypass capacitor (0.1 ~0.2 uF) as close as possible to ESD diode network power rail to shunt ESD current to both power rails
Maybe add Zener in parallel with capacitor to minimize parasitic inductance of bypass capacitor
ADD BYPASS CAPACITOR - Slide
Though power supplies have low output impedances at DC and low frequencies, at high frequencies, regulators can respond in 1-2 ns and have high impedances during a fast ESD current surge.
After removing inductance from the path of the ESD diode network and the power rail, also place a high frequency bypass capacitor as close as possible to the power rail of the ESD network, to shunt the ESD current to ground in addition to the positive power rail.
VIN = VF of diode + L (dIESD/dt) + VSUPPLY
where VSUPPLY = VDC + IESDxROUT ROUT is PS output Z
So for every Ohm of ROUT and Ampere of IESD current there is an additional Volt added to the ESD voltage that the device sees. To mitigate this effect, a ceramic capacitor of 0.1F to 0.2 F should be put between the two power rails. This should provide enought protection to meet the IEC Level 4 (8kV) requirements. Electrolytic capacitors should not be used because of their poor high frequency characteristics. Also keep the capacitor leads very short to reduce their inductance.
For extra protection, connect a Zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the Zener diode should be slightly higher than the maximum supply voltage.

20. Using a Series Resistor to Minimize Downstream Current
10-Nov-18
Using a Series Resistor to Minimize Downstream Current
Can be considered for latch-up sensitive applications
Guaranteed clamping voltage limits current downstream (I = V / R)
Only for inputs with high Z
Only for output drivers with low Z
watch out for filtering of signal
USING A SERIES RESISTOR TO MINIMIZE DOWNSTREAM CURRENT - Slide
An input series resistor gives added ESD protection, especially when the protected device is sensitive to latch-up. With a specified downstream clamping voltage you can set a current limit for the input of the device to be protected by inserting a current limiting resistor. However, this is only applicable to high impedance inputs so that no significant signal voltage dividing occurs over the series resistor and the input impedance of the circuit.
Although CMOS circuits have very high input impedances and can tolerate large series resistors, watch out that the series resistor combined with the input capacitance doesn't create a filter that degrades the signals edges.

21. 10-Nov-18
Power-down Issues
Diode protected systems that are powered down can drain current from an active high input through the diode to VCC
This can drain batteries and/or damage devices on the same line
To avoid this, isolate VCC from the bypass capacitor with a blocking diode
One diode solution
POWER DOWN ISSUES - Slide
One has to consider the issue of current flow through the upper diode going to Vcc when different parts of a system are powered down, but others are still powered. When that happens there is the possibility of draining batteries or more importantly, damaging devices. To avoid this, you can insert a blocking diode between the power pin of the ESD protection network and Vcc. Only one diode is needed for all protecting circuits in one package.

22. Component and System Specifications
10-Nov-18
Component and System Specifications
There is no simple formula to translate system specifications into component specifications
IEC Specification is more severe than HBM
Line capacitance and inductance shape the ESD pulse, reducing its peak value
Poor device placement can degrade performance
If there are multiple devices on a line, decide which to protect
The relationship between downstream clamp voltage and downstream protection is not exact
COMPONENT AND SYSTEM SPECIFICATIONS - Slide
In summary:
There is unfortunately, no simple way to translate system specifications into device specifications. We start by deciding on specific ESD requirements and which ESD model will be used. As we have seen earlier there are differences between a HBM spec and an IEC1000 specification. We must consider the parasitic impedances which shape, to a large degree, the ESD current pulse and its peak value. In many cases there may be multiple devices on a line, further modifying the ESD pulse that any device might see individually.
We have seen the influence component placement can have on system ESD protection, so that poor PCB layouts can negate some of the benefits of ESD protection devices.
Finally, the relationship between downstream clamping voltage and downstream protection is not exact.

23. 10-Nov-18
Validating the Design
Define the practical limits of functional failure (e.g. Data integrity, recovery time)
Test only at those places subject to touch during normal operation
Use Contact ES Discharges to coupling planes & conductive surfaces, I/O pins, flex pads, and power pins
Use Air ES Discharges to insulating surfaces, openings at edges of keys, flex cables, vent areas, seams, slots, apertures
VALIDATING THE DESIGN - Slide
It may not be possible to keep a system running under every conceivable set of ESD events. Therefore it is important to define practical limits of failure such as data integrity and/or recovery times.
Test only those places that are subject to touch during normal operation.
Contact Electro Static Discharges should be used for coupling planes and all conductive surfaces, I/O ports, power pins and the like
Air ES Discharges should be used for insulating surfaces, openings at keys, flex cables, vent areas, seams and slots etc

24. Total Solution Cost ESD failure is a question of statistics
10-Nov-18
Total Solution Cost
ESD failure is a question of statistics
One cannot eliminate all reliability issues
Goal is to minimize total solution cost
Cost of reliability
Cost of protection
Must find proper minimum
Total Cost of the Solution
Let's first recognize that ESD failures are largely a question of statistics. Second, improved ESD immunity should be looked at from a cost-benefit viewpoint. Moving from having no protection to providing 5kV of ESD protection (per HBM) provides significant cost benefits via reduced defect rates, higher reliability etc. But as you continue to improve the ESD protection, the marginal benefits will decrease while the cost to implement these improvements will continue to rise. These curves here support only a qualitative analysis but it is intuitive that there is an optimum situation with the lowest cost for the necessary level of ESD immunity.

25. Lightning vs. ESD 200MV 30kA 30us 15kV 45A 80nS
10-Nov-18
LIGHTING versus ESD Slide
Just so you don’t think that you have a difficult job in protecting against ESD, here is the energy of a lightning strike, which is many magnitudes worse than ESD, and there are engineers who have to design systems to protect against these zaps.
200MV 30kA 30us kV 45A 80nS