1. Deadlock Free Hardware Router with Dynamic Arbiter
Bharat Ramanathan
IEEE ISMS 2018, Kuala Lumpur – Malaysia
11/10/2018

2. Speaker Introduction Bharat Ramanathan Post-Graduate
Major: Electrical & Electronics Engg.
IEEE Member
Mumbai, India
11/10/2018

3. Overview of Presentation
Introduction
Scheduler Design
Odd - Even Routing Algorithm and its Rules
Router Design
Round Robin Arbiter - Programmable Priority Encoder (PPE) design
Priority Decider Circuitry (PDC) design
Delay Calculation and Result
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4. Introduction - Why NoC
Inter-core communication, challenge of SoC (System on Chip) designers
Conventional bus based architecture suffers from low throughput
NoC (Network on Chip) architecture - an improvement. Substantially higher throughput!
Node Degree - Number of interconnections among routers
Network Diameter - Number of hops to reach destination
Increased Node Degree - Decreases Network Diameter which improves Performance. But router itself is slower due to interconnect capacitances
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5. Introduction - Design Features
Square Mesh Interconnection
Wormhole Switching - Small Buffer sizes, Best throughput
But vulnerable to deadlocks
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6. Scheduler Design
Necessity – Multiple inputs and outputs are present while only one can be serviced per clock cycle
Multiple Input Buffer. Must decide which packet is routed
Priority based decision, better than first come first served
Priority updated every cycle
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7. Odd-Even Algorithm Necessary to prevent deadlocks and packet drops
Restricts a few turns depending on router location – effectively preventing deadlocks
Routers – Divided into two classes – odd column router and even column router. No 180 degree or 360 degree return of data permitted for both classes
Odd column router – ES and SW turns prohibited
Even column router - EN and NW turns prohibited
Certain connections not necessary in router design
Separate design for odd and even column router
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8. Router Design
Odd column router – ES,SW connection removed
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9. Router Design
Even column router – EN,NW connection removed
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10. PPE – Round Robin Arbiter Design
Consists of two priority encoders, or tree, and array, and gate , or gate
The upper priority encoder gives active priority requests, or tree gives high if priority line is not active
The bottom PE gives standard requests
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11. PDC – Priority Decider Circuit
Consists of DFF and logic gates – is a modified State Machine
Input is the active request and output sent to and array
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12. Delay Calculation and Result
Design delay was calculated for TSMC 180 nm process.
The hardware router performance was compared to a similar GPP in TSMC process.
The performance improvement ratio is 8.498
Design suitable for fixed communication protocol environment – Inter core communication
Inflexible to protocol changes
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13. Conclusion A hardware router was designed
Odd - Even algorithm was utilized to prevent deadlock and wormhole switching methodology was utilized to minimize buffer sizes
PPE and PDC circuits were designed and tested
The entire design delay was calculated in TSMC 180 nm process
Delay was compared to a GPP
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14. Thank You
11/10/2018