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Finite State Machines k State Transition Diagrams
Peter A. Smith & Alexander M. Fedorec
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Three Different Views of a System
Structural Model (e.g. entity, class, deployment diagrams...) Showing the components, subsystems, modules, entities or objects and how are they related/connected Functional Model (e.g. use case model, DFD, HIPO…) Showing the capabilities and functions required of the system. Normally expressed in terms of inputs, outputs and processes Behavioural Model (e.g. activity, state diagram…) Shows system dynamics. Represents how the system changes state/mode and the events and conditions that cause the changes to happen. A.M.Fedorec 10/11/ :25
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Systems Behaviour Systems can classified by the way they change:
Discrete Finite number of discrete internal states, Finite number of distinct inputs and outputs. Operates in discrete time steps Measures map to natural numbers (positive integers) Continuous Internal states, inputs and outputs continuously variable Measures map to the real numbers e.g. analogue watch vs. digital watch coins in a purse vs. fluid in a bottle? A.M.Fedorec 10/11/ :25
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Finite State Machines An FSM describes a system behaviourally as
Finite number of discrete states and Finite number of permissible transitions between states e.g. Traffic lights 3 lights each of which can be in one of two states (on or off) 8 possible states (all lights off, one on, any two on, all three on) Only 4 legitimate states and 4 valid transitions: Red on Red & Amber Green Amber on Red Can be modelled as “State Transition Graph” (STG)) States – labelled circles or rounded boxes. Each circle represents one possible state that the FSM can be in. Transitions – Arcs connecting states labelled with events that trigger state transitions Also known as Finite State Automata (FSAs) A.M.Fedorec 10/11/ :25
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Example FSM: Traffic Lights
All Possible States and Transitions And so on…. Red Red & Amber All lights off Green & Red All lights on Amber Green Green & Amber Q. Given 8 states how many possible transitions are there? A.M.Fedorec 10/11/ :25
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Example FSM: Traffic Lights
Valid States and Legal Transitions Red Red Red & Amber Red & Amber All lights off Green All lights off Green & Red All lights on Amber Amber Green Green & Amber A.M.Fedorec 10/11/ :25
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FSMs with Output: Transducers
State transitions are triggered by inputs or caused by events (e.g. pushing a button, a clock tick, change temperature) When machines change state they normally do something and the actions often generate output. Automata with input and output are sometimes called transducers because of their connection to electronics input/event shutdown POWER POWER idle help F1 state transition new state shutdown light off POWER POWER idle light on help Display “stay calm” F1 state output/action A.M.Fedorec 10/11/ :25
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Example FSM: Traffic Lights Valid States, legal transitions and output
Red light S2 Red + Amber State Output S1 Stop Red light S2 Ready Red + Amber lights S3 Go Green light S4 Caution Amber light Note: system greatly simplified. Real system will have input signals: Timing devices Pedestrian buttons Road induction loops Traffic cameras S3 Amber S4 Green A.M.Fedorec 10/11/ :25
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Other Example Finite State Machines
Car injection systems Communications systems Digital Computers Computer language translation e.g. from high level to machine code Electronic Games Fetch-execute cycle Operating systems Vending machines Washing machines A.M.Fedorec 10/11/ :25
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Input or state changing event (c )
Mealy & Moore Machines Transducer output can either be on the state nodes (“Moore machine” e.g. traffic lights example) or on the transition arcs (“Mealy machine”). Mealy and Moore machines can be shown to be equivalent: State (q4 ) Output or action (t) q4 t a c b a/t c/t b/t Input or state changing event (c ) A.M.Fedorec 10/11/ :25
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FSM with one input and one output.
FSM asserts its output (i.e. outputs a ‘1’) when it recognizes the input bit sequence: "1011". Machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. E.g. the input string = " " will cause the output to go high twice: = " " FSM implemented as a Moore Machine (output on state): S0 0 S1 0 S2 0 S3 0 S4 1 ...1 ...10 ...101 1 FSM implemented as a Mealy Machine (output on transition): S0 S1 S2 S3 ...1 ...10 ...101 0/0 1/1 1/0 A.M.Fedorec 10/11/ :25
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UML Notation For FSMs Active Idle Action on state
BACKGROUND INFORMATION FOR INTREST UML Notation For FSMs event Action disconnect Idle do: play dial tone Active off hook on hook Action on state A.M.Fedorec 10/11/ :25 Note UML is not part of the CSA syllabus
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UML Notation for FSMs “Statechart Diagrams”
BACKGROUND INFORMATION FOR INTREST UML Notation for FSMs “Statechart Diagrams” State transition State Initial State event Final State Action disconnect Idle Active off hook / play dial tone on hook Action on state transition A.M.Fedorec 10/11/ :25 Note UML is not part of the CSA syllabus
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Example Telephone Idle Talking PlayingDialTone Connecting Dialing
BACKGROUND INFORMATION FOR INTREST Example Telephone Idle Event/action on hook off hook / play dial tone Talking on hook PlayingDialTone digit connected digit on hook Dialing Connecting complete on hook Note UML is not part of the CSA syllabus A.M.Fedorec 10/11/ :25
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Nested States in UML Idle Active Talking PlayingDialTone Connecting
BACKGROUND INFORMATION FOR INTREST Nested States in UML Idle off hook / play dial tone Active Initial state PlayingDialTone Dialing Connecting Talking digit complete connected on hook Note UML is not part of the CSA syllabus A.M.Fedorec 10/11/ :25
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Next state, output given input = 0
State Tables 11/10/2018 A FSM can be expressed in tabular form as the (state, input) pairs in terms of the next state, and action for each e.g. A circuit starts takes as input a string of ‘0’s and ‘1’s. After it inputs its first ‘1’ it will output a ‘1’ on the second, fourth, sixth... ‘0’ it inputs until it inputs another ‘1’ when it will go back to the reset state. reset q1 q2 1/0 0/- 0/0 0/1 State Table Current state Input = 0 Input = 1 R R, - q1, 0 q1 q2, 0 R, 0 q2 q1, 1 State Table A FSM can be expressed in tabular form as the (state, input) pairs in terms of the next state, and action for each. Next state, output given input = 0 1 State Diagram A.M.Fedorec 10/11/ :25 A.M.Fedorec OOP107APIClasses
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FSM Example (to do on whiteboard)
A coffee vending machine dispenses coffee at 20p per cup. It accepts 5p, 10p and 20p coins No change is given Inexhaustible supply of water cups, coffee powder etc. Modifications: A return coins button may be pressed at any time Tea is dispensed at 25p per cup A.M.Fedorec 10/11/ :25
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Coffee Machine Example
Accept 5p, 10p or 20p coins, Dispense coffee when input 20p Refund if return coin button pressed 20p / coffee returnCoins / refund returnCoins / refund q0 Actions coffee machine dispenses coffee refund machine returns coins Events 5p customer enters 5p coin 10p customer enters 10p coin 20p customer enters 20p coin returnCoins customer presses ‘return’ button error 20p 10p q1 5p 5p / coffee q2 10p 10p / coffee InsufficientMoney q3 10p 5p 5p Input State 5p 10p 20p returnCoins q0 q1 q2 q0 , coffee q3 error q0 , refund Basic States q0 no money in machine q1 5p in machine q2 10p in machine q3 15p in machine error more than 20p in machine InsufficientMoney A.M.Fedorec 10/11/ :25
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Minimal Tables If given the same inputs two separate states produce the same outputs and take the system to the same next state then one is redundant Current state Input = 0 Input = 1 qa qb, 1 qc, 0 qb qa, 0 qb, 0 qc qa qc 1/0 0/1 qb 0/0 Two separate states Redundant Given same input Same next state and output qa qb 1/0 0/0 0/1 Current state Input = 0 Input = 1 qa qb, 1 qb, 0 qb qa, 0 A.M.Fedorec 10/11/ :25
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Subjects of State Diagrams in UML
BACKGROUND INFORMATION FOR INTREST ONLY Subjects of State Diagrams in UML All classifiers in UML have identity, state and behaviour and can therefore be represented by a statechart (however dumb entity objects may stay in only one state for their entire life, eg. a static string) Examples: Use Cases Student registering interest for a job with the IT placement office involves recording their details if it is the first time they have applied for a job Classes Student object changes from level 5 to sandwich placement or level 6 etc. Other Examples: Windows Edit-Paste is only valid if there is something in the clipboard Devices, Controllers, Transactions, Application, Coordinators A.M.Fedorec 10/11/ :25 Note UML is not part of the CSA syllabus
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Concurrent States in UML
BACKGROUND INFORMATION FOR INTREST Concurrent States in UML Idle maintain Maintenance Testing Testing devices Self Diagnosis Commanding Waiting Command keyPress [not continue] [continue] Note UML is not part of the CSA syllabus A.M.Fedorec 10/11/ :25
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Concurrent States in UML Example 2
BACKGROUND INFORMATION FOR INTREST ONLY Concurrent States in UML Example 2 © 2007 Pearson Education, Inc. Publishing as Pearson Addison-Wesley Note UML is not part of the CSA syllabus A.M.Fedorec 10/11/ :25
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Non-Deterministic FSA
In automata theory, a finite state machine is called a deterministic finite automaton (DFA), if each of its transitions is uniquely determined by its source state and input symbol, and reading an input symbol is required for each state transition. A nondeterministic finite automaton (NFA), or nondeterministic finite state machine, does not need to obey these restrictions. In particular, every DFA is also an NFA. P Q 1 0,1 Nondeterministic since in state p reading a 1 can lead to p or to q. From: Nondeterministic finite automaton, accessed Feb 2016 10/11/ :25
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Summary Systems have state
Events such as inputs cause the system to change state State change may trigger an output on the state transition or in the new state. A state transition graph describes the legal states and valid transitions a system can make This can also be described with a state table A.M.Fedorec 10/11/ :25
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Further Reading For Computer Scientists
Cohen, D., Introduction to Computer Theory 2e, Wiley, 1997 For Software Engineers Harel, D., Politi, M. Modeling Reactive Systems with Statecharts, McGraw-Hill, 1998 For CSNE Pedroni, V.A., Finite State Machines in Hardware: Theory and Design, MIT, 2013 For fun: Stefan Hollos, S., Hollos, J.R., Finite Automata and Regular Expressions: Problems and Solutions, Abrazol Publishing, 2013 10/11/ :25
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