1. Operational Amplifier Design
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CSE598A/EE597G Spring 2006
Operational Amplifier Design
Insoo Kim, Jaehyun Lim, Kyungtae Kang, Kyusun Choi
Mixed Signal CHIP Design Lab.
Department of Computer Science & Engineering
The Pennsylvania State University

2. 2 Stage OP Amp Design

3. 2 Stage OP Amp 11/11/2018 11/11/2018 Frequency Compensation
This is the basic schematic of 2 stage opamp that I used for standard library.
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4. [Reminder] Common Mode
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[Reminder] Common Mode
Common Mode Gain
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Before talking about the design of OP Amp, we need to know the concept of Common Mode. When two input pair is connected together, the input voltage is called Common Mode input voltage.
Common Mode Characteristics are related with two important performance of diff amp.
VSS+VTN1+VDSAT5+VDSAT1 < VIC < VDD–|VDSAT3|–|VTP3|+| VTN1|
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5. 2 Stage OP Amp Design Design Process Model Parameter Extraction (1/6)
kn : uA/V kp : uA/V2
n : p : 0.055
Vthn : V Vthp : V
Assign Current from Power Consumption Spec. (2/6)
Power Consumption : 2 mW
Total Current : 0.4 5V VDD
Input Pair : 0.2 mA
Second Stage : 0.2 mA
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6. 2 Stage OP Amp Design Design Process
Determine minimum channel length (3/6)
Determine channel width (4/6)
Determine W1,2 from voltage gain spec.
Determine W5 & Bias Voltage from power consumption & CM min.
Determine W3,4 from CM max.
Determine Bias Level of Current Source Tr. (5/6)
Considering CM min value and the transistor size
Check other specifications (6/6)
Repeat step 4 to 6
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7. A Calculation Example
Calculated Gain= 3000 (70dB)
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8. Simulation Results Gain: 59dB BW: 1.15 GHz This OP Amp is unstable!
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9. [Reminder] Feedback & Stability
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[Reminder] Feedback & Stability
However, when we configure feedback system, we should take special care about stability.
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10. Before Frequency Compensation
A unit gain buffer characteristic without frequency compensation + -
Vin
Vout
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11. Frequency Analysis
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12. (cont’d) Frequency Analysis
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13. Positive Zero & Pole-Zero Cancellation
Feed Forward
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14. Positive Zero & Pole-Zero Cancellation
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15. An Example of Frequency Compensation
Poles moved!
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16. After Frequency Compensation
A unit gain buffer characteristic with frequency compensation
Frequency compensated OP Amp + -
Vin
Vout
Frequency Compensation must be considered in designing OP Amps
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17. Basic Folded Cascode Design of Single Ended Folded Cascode
Folded Cascode Op Amp
Basic Folded Cascode
Design of Single Ended Folded Cascode

18. Cascode Stage
Small Signal Analysis
Rout
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19. Folded Cascode Stage Schematic Advantages Disadvantages
Wider Operating Range than telescopic cascode stage
Easy to set Common Mode Voltage
Disadvantages
Limited Output swing
Large Voltage Headroom
Large Power Consumption
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20. Single Ended Folded Cascode Op Amp
Circuit Configuration
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21. (cont’d) Single Ended Folded Cascode Op AmpGm
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22. (cont’d) Single Ended Folded Cascode Op Amp
Rout
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23. (cont’d) Single Ended Folded Cascode Op Amp
Design Process (1/3)
Model Parameter Extraction
kn : uA/V kp : uA/V2
n : p : 0.055
Vthn : V Vthp : V
Assign Current from Power Consumption Spec.
Total Current : mA
Input pair : mA
Current mirror : 0.25 mA
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24. (cont’d) Single Ended Folded Cascode Op Amp
Design Process (2/3)
Determine W3 from CM_min, CM_max Spec.
CM_min
CM_max
Determine W4~W7 and Bias2 from Vout_max Spec.
Vout_max :  Determine VB2
Assign Vdsat of M4,5 and M6,7 from Vout_max Spec
Eg) Vout_max=4V  Vdsat of M4,5= 0.6V, Vdsat of M6,7 = 0.4V
Calculate W4~7 to satisfy Vdsat & Ids of M4~7
Determine W8~W11 from Vout_min Spec.
Assign Vdsat of M8~M11 from Vout_min Spec.
Eg) Vout_min=0.8V  Vdsat of M8~11 = 0.4V
Calculate W8~11 to satisfy Vdsat and Ids of M8~11
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25. (cont’d) Single Ended Folded Cascode Op Amp
Design Process (3/3)
Determine W1,2 from Gain Spec.
Calculate Rout_tot
Calculate Required Gm value to satisfy Gain Spec.
Gain = Gm*Rout
Calculate W1,2 from Gm
Check other Spec. and Repeat the design process to optimize transistors size
Slew Rate
CM_min Check required
CMRR, PSRR
Check and Modify Bias Voltage to optimize transistor size.
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26. (cont’d) Single Ended Folded Cascode Op Amp
Frequency Analysis
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27. (cont’d) Single Ended Folded Cascode Op Amp
Design Example
39.75
89.7
53.1
68.1
3.54V
1.0V
80.25
3.14V
Calculated Gain= 3000 (70dB)
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28. (cont’d) Single Ended Folded Cascode Op Amp
Simulation Result
Gain: 68dB
BW: 170MHz
Loading: 2pF
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29. Folded Cascode Op Amp with CMFB
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30. Slew Rate Enhanced Folded Cascode Op Amp
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31. References
Joongho Choi, “CMOS analog IC Design,” IDEC Lecture Note, Mar
B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001.
Hongjun Park, “CMOS Analog Integrated Circuits Design,” Sigma Press, 1999.
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