1. Synthesis and Exploration of Multi-Level, Multi-Perspective Architectures of Automotive Embedded Systems
Jordan A. Ross
June 10th, 2016

2. Background & Motivation
Wants to design the power window E/E architecture
Design Decisions
Design Constraints
Design Objectives
With Respect To
Emily
Creates E/E Architectural Model with Variability
Synthesize
Candidate Architectures
Visualizes Candidates and Tradeoffs
TODO:
Update figure:
Change John to Emily (everywhere)
Change how I use the downward arrows
Change wording to align with new paper definitions
Where does synthesis fit it?
Expresses
Possible Candidate Architectures

3. Wants to design the power window E/E architecture
Design Decisions
Design Constraints
Design Objectives
With Respect To
Emily
Creates E/E Architectural Model with Variability
Synthesize
Candidate Architectures
Visualizes Candidates and Tradeoffs
Expresses
Possible Candidate Architectures

4. How Are E/E Architectures Modeled Today?
EAST-ADL was developed for the purposed of modeling these architectures.
Not all OEM’s use EAST-ADL but rather have a similar approach.
TODO:
Say something about how modeling architectures is currently done today? See previous iteration of presentation.

5. Our Reference Model for Early Design
System
Perspectives
Feature Model
Functional Analysis Architecture …
Variability
Latency
Mass
Parts Cost
Warranty Parts Cost
Multi-Layer
Hardware Design Architecture
Device Node Classification
Power Topology
Communication Topology
Multi-Perspective

6. The Reference Model Components
System
Feature: Functionality or design choice visible to the end-user.
Feature Model
Functional Analysis Architecture
Hardware Design Architecture
Device Node Classification
Power Topology
Communication Topology

7. Emily’s Power Window Example
Driver PW
Basic Up Down
Express Up
Express
Express Down
Feature Model Legend
Feature
Mandatory
Exclusive Features

8. The Reference Model Components
System
Analysis Function: A function for control logic either in hardware or software.
Functional Device: A function for reading inputs or generating output. Can be either hardware or software.
Function Connector: A logical connection between analysis functions/functional devices.
Feature Model
Functional Analysis Architecture
Hardware Design Architecture
TODO:
- Update definitions based on paper
Device Node Classification
Power Topology
Communication Topology

9. Emily’s Power Window Example
Legend:
Functional Device
Analysis Function
Function Connector
DriverWinSysFAA
WinSwitch
WinMotor
CurrentSensor
WinArbiter
WinControl
PinchDetectionFAA
PositionSensor
PinchDetection
position
object
localWinReq
winReq
winCmd
current HW SW

10. The Reference Model Components
System
Feature Model
Functional Analysis Architecture
Device Node:
Physical nodes in the architecture.
Has a type – smart, e/e, or power.
Hardware Design Architecture
Device Node Classification

11. The Reference Model Components
Device Node
Power Device Node
E/E Device Node
Smart Device Node
Analysis Function
Functional Device
Software Functional Device
Hardware Functional Device
Software Analysis Function
Hardware Analysis Function
-deployedTo

12. The Reference Model Components
Device Node A
Device Node B
Level of Abstraction
Legend:
Port
Pin
System
Discrete Data Connector: A connector used to indicate the status of a binary input, such as a switch.
Analog Data Connector: A connector which typically sends an analog signal (as opposed to digital); typically encoded in voltage amplitude.
Bus Connectors: Connector between two or more nodes in which the nodes can serially pass messages.
Feature Model
Functional Analysis Architecture
Hardware Design Architecture
Communication Topology

13. Emily’s Power Window Example
DriverWinSysCT
Switch
Motor
DoorModule
BCM
Legend:
Bus
Bus Connection
Discrete Data Connector
Local Device Node
Remote Device Node
Smart Device Node

14. The Reference Model Components
System
Feature Model
Functional Analysis Architecture
Hardware Design Architecture
Device Power Connectors: An abstract connector for a higher gauge wire for distributing lower voltage.
Load Power Connectors: An abstract connector for a lower gauge wire for distributing higher voltage.
Power Topology

15. Emily’s Power Window Example
Switch
Motor
DoorModule
DoorInline
BCM EC
Vcc
DriverWinSysPT
Legend:
Load Power Connector
Device Power Connector

16. The Reference Model Components
System
Feature Model
Analysis functions and functional devices are deployed to device nodes.
Function connectors are deployed to the communication topology connectors.
Currently, power is not modeled at the functional level thus is not deployed.
Functional Analysis Architecture
Hardware Design Architecture
Device Node Classification
Power Topology
Communication Topology

17. Capturing Variability
System
Feature Model
Functional Analysis Architecture
Hardware Design Architecture
Device Node Classification
Communication Topology
Power Topology
Feature Presence
Function Presence
Function Connector Presence
Function Implementation Choice
Function Deployment
Function Connector Deployment
Device Node Type
Device Node Presence
Connector Source and Target
Connector Presence
Bus Type
Connector Presence
Connector Endpoints

18. Emily’s Power Window Example
Driver PW
Basic Up Down
Express Up
Express
Express Down
DriverWinSysFAA
WinSwitch
WinMotor
CurrentSensor
WinArbiter
WinControl
PinchDetectionFAA
PositionSensor
PinchDetection
position
object
localWinReq
winReq
winCmd
current HW
HW/SW SW
Feature Model Legend
Feature
Optional
Mandatory
Exclusive Features

19. Capturing Latency System Feature Model
Functional Analysis Architecture
Hardware Design Architecture
Device Node Classification
Communication Topology
Power Topology
Form timing chains using functions and function connectors
Assign latencies to functional devices and analysis functions
Assign message sizes to function connectors
WinSwitch
WinMotor
CurrentSensor
WinArbiter
WinControl
PinchDetectionFAA
PositionSensor
PinchDetection
position
object
localWinReq
winReq
winCmd
current
Message Size = 1 byte
Deployed to smart node affects function latency
Deployed to hardware connector affects function connector latency
Make note that this is not a constraint. Just stating some properties about the system.
Latency = 10ms
Assign speed factors to smart nodes
Different communication connectors have different transfer rates.

20. Capturing Mass, Parts Cost, and Warranty Parts Cost
RQ1: What aspects of our reference model are unique and not found in current meta-models for E/E architecture? Or are found but not supported by reasoning?
System
Feature Model
Functional Analysis Architecture
Hardware Design Architecture
Device Node Classification
Communication Topology
Power Topology
Mass
Assign lengths to hardware connectors
Multiplicative factor for unit length mass for each connector type.
Assign mass to device nodes.
Cost
Multiplicative factor for unit length cost for each connector type.
Assign cost to device nodes.
Warranty Cost
Assign replacement cost to device nodes.
Assign failure rate in PPM

21. Wants to design the power window E/E architecture
Design Decisions
Design Constraints
Design Objectives
With Respect To
Emily
Creates E/E Architectural Model with Variability
Synthesize
Candidate Architectures
Visualizes Candidates and Tradeoffs
Expresses
Possible Candidate Architectures

22. Some Example Design Exploration Scenarios
Emily would like to investigate the possibility of adding a dedicated ECU to each door (we call the door module). Precisely, she would like to find out if it is a cost effective solution while meeting the requirements for mass and latency.
Emily would like to know if it is possible to implement the express up feature on their current setup while satisfying latency constraints. If so, she would like to find out what designs they would be.
Emily would like to compare having a dumb architecture which uses electric/electronic switches and motors versus a smart architecture where they are smart. She would like to explore optimal designs of both to see how they compare in respect to the qualities: mass, parts costs, and warranty parts cost.
OPTIONAL:
- Include why manually exploring candidates does not work as well.

23. Some Example Design Exploration Scenarios
Emily is tasked with designing the power window for a higher end car in which cost is irrelevant but mass should be minimized, she would like to explore the possible designs. Additionally, since its a high end car, all features should be included. Lastly, the end-to-end latency for pinch detection to react and reverse the motor should be less than 200 ms.
Emily would like to minimize the cost, regardless of the features to support an “economy class” vehicle her company is rolling out. Is there an optimal car design that does include all features?
Emily is investigating whether it would be better in terms of all qualities (latency, mass, parts cost, and warranty parts cost) to have a distributed architecture, when considering multiple power window systems (i.e., the driver and passenger doors), or a centralized one.
OPTIONAL:
- Include why manually exploring candidates does not work as well.

24. Defining Design Space Exploration
Design Space Exploration: The activity of discovering and evaluating design alternatives, captured by design specifications, during system development (adapted from [1]).
Design Specification: A set of one or more design decisions, constraints, and objectives joined together by Boolean logic formed over a architectural model to specify the desired candidate architectures.
Design Decision: A restriction on the variability allowed by a concrete component in the modeled architecture.
Design Constraint: A restriction of the value for a system or concrete component quality in the modeled architecture such as mass or latency.
Design Objective: An optimization goal for a system quality in the modeled architecture in which to maximize or minimize.
[1] Kang, E., Jackson, E., Schulte, W.: An approach for effective design space exploration. In: Foundations of Computer Software. Modeling, Development, and Verification of Adaptive Systems, pp. 33–54. Springer (2010)

25. What Design Decisions Can We Make?
System
Feature “ExpressUp” is in the architecture.
“WinArbiter” function is implemented in hardware.
The “Switch” device node is smart
The “DoorModule” device node is present in the architecture
The “winCmd” function connector uses the “localDoorBus” bus connector to communicate. ….
Feature Model
Functional Analysis Architecture
Variability
Hardware Design Architecture
Device Node Classification
Power Topology
Communication Topology
Combine the system model with variability

26. What Design Constraints and Objectives Can We Have?
System
Feature Model
The end to end latency for the timing chain from the “WinSwitch” function to the “WinMotor” function is less than 500 ms.
Minimize the total mass of the system …
Functional Analysis Architecture
Latency
Mass
Parts Cost
Warranty Parts Cost
Hardware Design Architecture
Device Node Classification
Power Topology
Communication Topology
Combine the system model with quality perspectives

27. Generalizing the Possible Specifications
make sure to state that this is not the complete possibilities

28. Example
RQ2: Are there design exploration scenarios in which considering our reference model we can consider while others can not?
Emily is tasked with designing the power window for a higher end car in which cost is irrelevant but mass should be minimized, she would like to explore the possible designs. Additionally, since its a high end car, all features should be included. Lastly, the end-to-end latency for pinch detection to react and reverse the motor should be less than 200 ms.
Feature “ExpressUp” is in the architecture AND The end-to-end latency for timing chain PinchDetection_TC must be less than 200 ms AND Minimize the total mass of the architecture
TODO: Add animation.

29. Wants to design the power window E/E architecture
Design Decisions
Design Constraints
Design Objectives
With Respect To
Emily
Creates E/E Architectural Model with Variability
Synthesize
Candidate Architectures
Visualizes Candidates and Tradeoffs
Now we want to visualize. To do this we need to now discuss what we used to encode the model and encode the specifications
Expresses
Possible Candidate Architectures

30. How Is This All Possible?
Wants to design the power window E/E architecture
Emily
Creates E/E Architectural Model with Variability
Chocosolver
Synthesize
Candidate Architectures
Visualizes Candidates and Tradeoffs
Clafer Web Tools

31. Visualizing Tradeoffs With Clafer Web Tools
Emily would like to investigate the possibility of adding a dedicated ECU to each door (we call the door module). Precisely, she would like to find out if it is a cost effective solution (in terms of unit & warranty cost) while meeting the requirements for mass and latency.
TODO:
Show an example visualization for the design specification.

32. Visualizing Tradeoffs With Clafer Web Tools
RQ3: Does considering a subset of the reference model layers opposed to considering all provide a significantly different result/tradeoff?
TODO:
Show an example visualization for the design specification.

33. Case Studies

34. Power Window Feature Model
Driver Power Window
Basic
Up / Down
Express Up
Express Down
Passenger Power Window
Basic Up / Down
implies

35. Door Locks Feature Model
Outside Door Handle Sensor
Basic
Door Locks
Remote Key Access
Passive Key Entry
Lock Switch Position
Speed Smart Lock
Individual Lock Switch
Central Lock Switch
implies
Button Sensor
Capacitive Sensor

36. Model Sizes
Single – 32,000
Two door – Over 650 million candidates

37. How Does Our Approach Compare?
Dedicated door ECU vs. no door ECU
RQ1: What aspects of our reference model are unique and not found in current meta-models for E/E architecture? Or are found but not supported by reasoning?
RQ1 Answer: Features, variability at all layers, function implementation, discrete/analog connectors, and power topology
Possible to implement express up feature
Dumb vs. Smart
AAOL – Automotive Architecture Optimization Language
High-end car
Economy car
Distributed vs. Centralized

38. Taking a Closer Look at Scenario 6…
Emily would like to minimize the cost, regardless of the features to support an “economy class” vehicle her company is rolling out. Is there an optimal car design that does include all features?
RQ2: Are there design exploration scenarios in which considering our reference model we can consider while others can not?
RQ2 Answer: Yes!

39. What About Slicing Out Layers?
How does the power topology affect the overall architecture?
DriverWinSysPT
WinControl
Switch
DoorInline
BCM
DriverWinSysPT
Switch
DoorInline
BCM
Motor
DoorModule EC
WinControl Deployed to the BCM
Motor
DoorModule EC
WinControl
WinControl Deployed to the Motor

40. What About Slicing Out Layers?
RQ3: Does considering a subset of the reference model layers opposed to considering all provide a significantly different result/tradeoff?
With the Power Topology
RQ3 Answer: Yes, we can have some cases where slicing hides potential tradeoffs!
RQ4: Is it even feasible to ask the individual design decisions, constraints, and objectives shown earlier?
RQ5: Is it feasible to ask the 6 design scenarios when considering the single and two door power window model?
Without the Power Topology

41. Looking at the Chocosolvers Performance
RQ4 Answer: The majority are feasible however, there are issues in when trying to find all optimal solutions.
TODO:
Invesitgate timesouts for DD14 and DC8

42. Looking at the Chocosolvers Performance
RQ5 Answer: It is feasible when considering the single door power window, however not for the two door case.

43. Conclusion
Presented a reference model for early design of E/E architectures.
Showed how the reference model can be used to model a power window architecture that expresses millions of candidate designs.
Highlighted where our approach surpasses current tooling.
Room for future work..
Scaling Chocosolver in order to model many systems.
Extending our reference model to accommodate fault tolerant architectures.
Refining the early design candidates to detailed designs.

44. Thanks for Listening! Questions?