1. MICROPROCESSOR MEMORY ORGANIZATION
Chapter 3
MICROPROCESSOR
MEMORY ORGANIZATION

2. Outline 3.1 Introduction 3.2 Main memory
3.3 Microprocessor on-chip memory management unit and cache

3. 3.1 Introduction
A memory unit is an integral part of any microcomputer, and its primary purpose is to hold instructions and data.
Memory system can be divided into three groups:
1. Microprocessor memory
2. Primary or main memory
3. Secondary memory

4. 3.1 Introduction
Microprocessor memory is a set of microprocessor registers, used to hold temporary results
Main memory is the storage area in which all programs are executed, include ROM & RAM
Secondary memory devices such as hard disks, also called virtual memory.
The microcomputer cannot execute programs stored in the secondary memory directly, so to execute these programs the microcomputer must transfer them to its main memory by a program called the operating system.

5. Microprocessor memory
3.1 Introduction
Microprocessor memory
main memory
Secondary memory
The fastest
The slower
The slowest
The smallest
The Largest
The larger

6. 3.2 Main memory
An important characteristic of a memory is whether it is volatile or nonvolatile.
The contents of a volatile memory are lost if the power is turned off.
On the other hand, a nonvolatile memory retains its contents after power is switched off.
ROM is a typical example of nonvolatile memory. RAM is a volatile memory.

7. Types of Semiconductor Memory Devices
Random Access Memory (RAM)
A memory device that can be read and written.
Volatile: It looses its data when the power supply is switched-off
When the supply is switched-on it contains random data
Used to store
User programs that are loaded from a secondary memory (disk)
Temporary data used by programs such as variables and arrays.
A RAM device can be
Static
dynamic
Read Only Memory (ROM)
A memory device that maintains its data permanently (or until the device is reprogrammed).
Non-volatile: It maintains its data even without power supply.
Used to store
Programs such as the BIOS.
Data such as look tables
A ROM device can be
Masked ROM (Programmed by the manufacturer)
Programmable ROM (can be program-erased-reprogrammed many times

8. Memory Types ROM (Read only memory) RAM (Random access memory):
PROM (programmable)
EPROM (Erasable programmable)
EEPROM (Electronically erasable programmable)
RAM (Random access memory):
SRAM (Static RAM)
DRAM (Dynamic RAM)

9. 3.2.1 Read-only Memory
PROM : a memory chip on which the write operation of data can be performed only once. PROM is reliable and stores the data permanently without making any change in it. It is mostly used in video games and electronic dictionaries.
EPROM: is a type of ROM in which data can be erased or destroyed using Ultraviolet Light.
EEPROM: a type of ROM in which data can be erased or destroyed by exposing it to an electric charge.
Flash ROM: a type of EEPROM that stores the information using floating-gate transistors, which can store electric charge for a longer period of time as compared to the normal transistors. This memory is mainly used in the memory cards of mobile phones, digital cameras and ipods for storing data.
Flash ROM has faster speed of reading data, as compared to any other type of ROM.

10. 3.2.2 Random Access Memory
Random Access Memory (RAM) is a volatile memory and loses all its data when the power is switched off.
It is the main memory of the computer system that stores the data temporarily and allows the data to be accessed in any order.
RAM can be categorized into two main types, namely, Static RAM and Dynamic RAM.

11. Random Access Memory
Static RAM: is a type of RAM in which data is stored till the power of the computer system is switched on. SRAM uses a number of transistors to store a single bit of digital information.
Dynamic RAM: is the RAM in which data is stored in a storage cell, consisting of a transistor and a capacitor. The DRAM needs to be continuously refreshed with power supply because the capacitor has the tendency to get discharged. DRAM retains the data for a very short span of time, even after the power supply is switched off.

12. 3.2.2 Random-Access Memory
There are two types of RAM: static RAM (SRAM), and dynamic RAM (DRAM).
SRAM
DRAM
stores data in flip-flops.
stores data in capacitors.
memory does not need to be refreshed.
it can hold data for a few milliseconds, need to be refreshed
have lower densities
have higher densities
DRAMs are inexpensive, occupy less space, and dissipate less power than SRAMs.

13. Main Memory Array Design
Two-dimensional array of bit cells
Each bit cell stores one bit
An array with N address bits and M data bits:
2N rows and M columns
Depth: number of rows (number of words)
Width: number of columns (size of word)
Array size: depth × width = 2N × M

14. Memory Array: Example 22 × 3 - bit array Number of words: 4
• Word size: 3-bits
• For example, the 3-bit word stored at address 10 is 100

15. 3.3.1 Memory Management Concepts
Memory Management Unit (MMU):
a device, located between the microprocessor and memory, to control accesses, perform address mappings, and act as an interface between the logical (programmer’ memory) and physical (microprocessor’s directly addressable memory) address spaces.

16. 3.3.1 Memory Management Concepts
MMU address translation:
It translates logical program addresses to physical memory address. Note that in assembly language programming, addresses are referred to by symbolic names.
These addresses in a program are called logical addresses because they indicate the logical positions of instructions and data.

17. Memory Mapping Mapping is performed by memory management units
Memory mapping is implemented by the MMU(s) using page (translation) tables stored in memory
The OS is responsible for defining the mappings, by managing the page tables.

18. Memory Mapping Typically divide the virtual address space into pages
Usually power of 2
The offset (bottom n bits) of the address are left unchanged
The upper address bits are the virtual page number

19. Address Mapping Function (Review)

20. Unmapped Pages The mapping is sparse. Some pages are unmapped.
Why are some pages unmapped?
Processes get a large amount of virtual address space each, but in practice they only use a tiny amount. Constructs like the stack and heap are places far away from each other.
Why are some pages unmapped?
Processes get a large amount of virtual address space each, but in practice they only use a tiny amount. Constructs like the stack and heap are places far away from each other.

21. Unmapped Pages
Pages may be mapped to locations on devices and others to both.

22. MMU Function
MMU translates virtual page numbers to physical page numbers via Translation Lookaside Buffer (TLB)
If TLB lacks translation, slower mechanism is used with page tables
The physical page number is combined with the page offset to give the complete physical address

23. MMU Function

24. MMU Function Computes address translation
Uses special associative cache (TLB) to speed up translation
Falls back on full page translation tables, in memory, if TLB misses
Falls back to OS if page translation table misses
Such a reference to an unmapped address causes a page fault

25. MMU Function If page fault caused by a CPU (MMU)
Enters the OS through a trap handler
If page fault caused by an I/O device (IOMMU)
Enters the OS through an interrupt handler

26. 3.3.1 Memory Management Concepts
MMU address translation:
The MMU can perform address translation in one of two ways:
1. By using the substitution technique.
2. By adding an offset to each logical address to obtain the corresponding physical address.

27. 3.3.1 Memory Management Concepts
MMU address translation:
Address translation using the substitution technique is faster than translation using the offset method. However, the offset method has the advantage of mapping a logical address to any physical address as determined by the offset value.

28. 3.3.1 Memory Management Concepts
MMU address translation:
Memory is usually divided into small manageable units: page and segment.
Paging divides the memory into equal sized pages; segmentation divides the memory into variable-sized segments.
It is relatively easier to implement the address translation table if the logical and main memory spaces are divided into pages.

29. 3.3.1 Memory Management Concepts
MMU address translation (mapping):
There are three ways to map logical addresses to physical addresses:
paging,
segmentation,
and combined paging-segmentation.

30. 3.3.1 Memory Management Concepts
The paging method
The virtual memory system is managed
by both hardware and software. The hardware included in the memory management unit handles address translation.
The memory management software in the operating system performs all functions, including page replacement policies to provide efficient memory utilization.

31. Paging Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 M bytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames.
To run a program of size N pages, need to find N free frames and load program
Internal fragmentation
Set up a page table to translate logical to physical addresses.

32. Fragmentation
Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used.
External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together in one large block
Compaction is possible only if relocation is dynamic, and is done at execution time

33. 3.3.1 Memory Management Concepts
The Segmentation method
an MMU utilizes the segment selector to obtain a descriptor from a table in memory containing several descriptors.
A descriptor contains the physical base address for a segment, the segment’s privilege level, and some control bits.

34. 3.3.1 Memory Management Concepts
The Segmentation method
When the MMU obtains a logical address from the microprocessor, it first determines whether the segment is already in physical memory.
If it is, the MMU adds an offset component to the segment base component of the address obtained from the segment descriptor table to provide the physical address.
The MMU then generates the physical address on the address bus for selecting the memory.

35. 3.3.1 Memory Management Concepts
The paged-segmentation method
each segment contains a number of pages. The logical address is divided into three components: segment, page, and word.
A page component of n bits can provide up to 2npages.
A segment can be assigned with one or more pages up to maximum of 2n pages; therefore, a segment size depends on the number of pages assigned to it.

36. Combined paging and segmentation
User address space is broken up into a number of segments, at the discretion of the programmer.
Each segment is broken up into a number of fixed size pages, which are equal in length to a main memory frame.
From the programmer point of view an logical address still consists of a segment number and an segment offset
From the system point of view, the segment offset is seen as a page number and a page offset for a page within the specified segment

37. 3.3.1 Memory Management Concepts
The Virtual memory
The key idea behind the virtual memory is to allow a user program to address more locations than those available in a physical memory.
An address generated by a user program is called a virtual address

38. 3.3.2 Cache Memory Organization
The performance of a microprocessor system can be improved significantly by introducing
a small, expensive, but fast memory between the microprocessor and main memory.

39. 3.3.2 Cache Memory Organization
a cache memory is very small in size and its access time is less than that of the main memory by a factor of 5. Typically, the access times of the cache and main memories are 100 and 500 ns, respectively.
A cache hit means : reference is found in the cache,
A cache miss means : reference is not found in the cache,

40. 3.3.2 Cache Memory Organization
The relationship between the cache and main memory blocks is established using mapping techniques.
Three widely used mapping techniques are
direct mapping,
fully associative mapping, and
set-associative mapping.

41. 3.3.2 Cache Memory Organization
Direct mapping,
Direct mapping uses a RAM for the cache. The microprocessor’s 12-bit address is divided into two fields, an index field and a tag field. Because the cache address is 8 bits
wide (28 = 256), the low-order 8 bits of the microprocessor’s address form the index field, and the remaining 4 bits constitute the tag field.
In general, if the main memory address field is m bits wide and the cache memory address is n bits wide, the index field will then require n bits and the tag field will be (m - n )

42. 3.3.2 Cache Memory Organization
Direct mapping,
The microprocessor first accesses the cache. If there is a hit, the microprocessor accepts the 16-bit word from the cache.
In case of a miss, the microprocessor reads the
desired 16-bit word from the main memory, and this 16- bit word is then written to the cache.
A cache memory may contain instructions only (Instruction cache) or data only (data cache) or both instructions and data (unified cache).

43. 3.3.2 Cache Memory Organization
Numerical example for Direct mapping

44. 3.3.2 Cache Memory Organization
Example : (Direct mapping) as in the previous figure
The content of index address 00 of cache is tag = 0 and data = 0 13F.
Suppose that a microprocessor wants to access the memory address 100.
The index address 00 is used to access the cache. Memory address tag 1 is compared with cache tag 0. This does not produce a match. Therefore, the main memory is accessed and the data is transferred into the microprocessor. The cache word at index address 00 is then replaced by a tag of 1 and data of

45. 3.3.2 Cache Memory Organization
One of the main drawbacks of direct mapping is that numerous misses may occur if two or more words with addresses that have the same index but different tags are accessed several times.

46. 3.3.2 Cache Memory Organization
Fully associative mapping
The fastest and most expensive cache memory
Each element in associative memory contains a main memory address and its content (data).

47. 3.3.2 Cache Memory Organization
Fully associative mapping When the microprocessor generates a main memory address, it is compared associatively (simultaneously) with all addresses in the associative memory. If there is a match, the corresponding data word is read from the associative cache memory and sent to the microprocessor. If a miss occurs, the main memory is accessed and the address and its corresponding data are written to the associative cache memory.

48. 3.3.2 Cache Memory Organization
Fully associative mapping

49. 3.3.2 Cache Memory Organization
Fully associative mapping Each word in the cache is a 12-bit address along with its 16-bit contents (data). When the microprocessor wants to access memory, the 12-bit address is placed in an address register and the associative cache memory is searched for a matching address. Suppose that the content of the microprocessor address register is 445. Because there is a match, the microprocessor reads the corresponding data OFAl into an internal data register.

50. 3.3.2 Cache Memory Organization
Set-associative mapping.
a combination of direct and associative mapping.
cache word stores two or more main memory words using the same index address. Each
main memory word consists of a tag and its data word. An index with two or more tags and data words forms a set
Cache is divided into a number of sets
Each set contains a number of lines
A given block maps to any line in a given set

51. 3.3.2 Cache Memory Organization
Set-associative mapping.
When the microprocessor generates a memory request, the index of the main memory address is used as the cache address. The tag field of the main memory address is then compared associatively (simultaneously) with all tags stored under the index.
If a match occurs, the desired dataword is read.
If a match does not occur, the data word, along with its tag, is read from main memory and written into the cache.

52. 3.3.2 Cache Memory Organization
How to write on cache :
There are two ways of writing into cache: the write- back and write-through methods.

53. 3.3.2 Cache Memory Organization
The write-back method
Whenever the microprocessor writes something into a cache word, a “dirty” bit is assigned to the cache word. When a dirty word is to be replaced with a new word, the dirty word is first copied into the main memory before it is overwritten by the incoming new word.
The advantage of this method is that it avoids
unnecessary writing into main memory.

54. 3.3.2 Cache Memory Organization
The write-through method,
whenever the microprocessor alters a cache address, the same alteration is made in the main memory copy of the altered cache address.
This policy is easily implemented and ensures that the contents of the main memory are always valid. This feature is desirable in a multiprocesssor system, in which the main memory is shared by several processors.

55. 3.3.2 Cache Memory Organization
A valid bit used to ensures proper utilization of the cache.
It is an extra bit contains in the tag directory
When the power is turned on, the valid bit corresponding to each cache block entry of the tag directory is reset to zero. This is done to indicate that the cache block holds invalid data.
When a block of data is transferred from the main memory to a cache block, the valid bit corresponding to this cache block is set to 1.

56. 3.3.2 Cache Memory Organization
Finally, microprocessors such as the Intel Pentium I1 support two levels of cache, L1 (level 1) and L2 ( level 2) cache memories.
The L1 cache (smaller in size) is contained
inside the processor chip while the L2 cache (larger in size) is interfaced external to the
microprocessor.

57. 3.3.2 Cache Memory Organization
The L 1 cache normally provides separate instruction and data caches. The processor can access the L1 cache directly and the L2 cache normally supplies instructions and data to the L1 cache.
The L2 cache is usually accessed by the microprocessor only if L 1 misses occur. This two-level cache memory enhances microprocessor performance.