1. CSE 140 Lecture 12 Combinational Standard Modules
CK Cheng
CSE Dept.
UC San Diego

2. Part III. Standard Modules
Interconnect Modules:
1. Decoder, 2. Encoder
3. Multiplexer, 4. Demultiplexer

3. Multiplexer
Definition
Logic Diagram
Application

4. Interconnect: Decoder, Encoder, Mux, DeMux
Processors P1
Memory Bank
Mux P2 Pk
Demux
Decoder
Data
Address
Address k
Address 2
Address 1
Data 1
Data k
Arbiter n
n-m m 2m
Decoder: Decode the address to assert the addressed device
Mux: Select the inputs according to the index addressed by the control signals

5. iClicker: Multiplexer Definition
A device that interleaves two or more activities
A communications device that combines several signals for transmission over a single medium
A logic circuit that sends one of several inputs out over a single output channel.
The circuit that uses a common communications channel for sending two or more messages or signals.
All of the above

6. 3. Mux (Multiplexer) Definition: A digital module that selects one of data inputs according to the binary address of the selector. E y
D2n-1-D0
(Data input)
Sn-1,0
(Selector or Address)
Description
If E = 1
y = Di where i = (Sn-1, .. , S0)
Else
y = 0

7. Multiplexer (Mux): Definition
Selects between one of N inputs to connect to the output.
log2N-bit select input – control input
E: Enable
y: Output
S: Selector or Address D0 D1 1
Data input

8. Multiplexer (Mux): Definition
Selects between one of N inputs to connect to the output.
log2N-bit select input – control input
Example: :1 Mux

9. PI Q: What is the output of the following MUX? 1 Can’t say1
Can’t say
E =1 y
S=1 1

10. Multiplexer Definition: 4-input muxEn D0 S1 S0 y D1 1 y D2 2 D3 3 S1 S0

11. Multiplexer: Logic Diagram
Logic gates
Sum-of-products
Tristates
For an N-input mux, use N tristates
Turn on exactly one to select the appropriate input

12. Multiplexer Application: universal set {Mux}
We use selector to decompose the function into smaller functions (less number of variables), which follows Shannon’s expansion.
We simplify the decomposed functions using K-map, which follows consensus theorem.

13. Multiplexer Application
Mux for a Boolean function with truth table as input
Building blocks of FPGA (Field Programmable Gate Array).
iClicker: For the logic diagram on left, output Y is AB
(AB)’
A+B
(A+B)’
None of the above

14. Multiplexer Application: universal set {Mux}
Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux. id
abc f
000 1
001 2
010 - 3
011 4
100 5
101 6
110 7
111 En y a b c S2 S1 S0 1 2 3 4 5 6 7

15. Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.y a b S1 S0 1 2 3 ab
c=0
c=1 D 00 D0 01 D1 10 D2 11 D3

16. Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2-input Muxes.00 01 10 11
D(b,c) 1 - D0 D1 E 1 a y

17. Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2-input Muxes.00 01 10 11
D(b,c) 1 - D0 D1 E b’ 1 a y
D0 (b,c) = b’
D1 (b,c) = bc
c=0 1 -
c=1
b=0
b=1
c=0
c=1 1
b=0
b=1
D1 (b,c)

18. Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2-input Muxes.
D1 (b,c)
b\c 1 D
D0=
D1= E b’ 1 a y

19. Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2-input Muxes.
D1 (b,c)
b\c 1 D
D0=0
D1=c E b’ 1 a b y c

20. Example 4: Given f (a,b,c) = Σm (0,2,4,7) + Σd(3,5), implement with 2-input Muxes.00 01 10 11 D 1 - D0 D1 E 1 a y
D0(b,c)
D1(b,c)

21. 4. Demultiplexers E yi = x if i = (Sn-1, .. , S0) & E=1
yi = 0 otherwise
y2n-1 -y0 x
S(n-1,0)
Control Input

22. Shifters
Logical shifter: shifts value to left or right and fills empty spaces with 0’s
Ex: >> 2 = 00110
Ex: << 2 = 00100
Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb).
Ex: >>> 2 = 11110
Ex: <<< 2 = 00100
Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end
Ex: ROR 2 = 01110
Ex: ROL 2 = 00111

23. Shifter s d xn x0 x-1 xn-1 yn-1 y0 s / n l / r
yi = xi-1 if E = 1, s = 1, and d = L
= xi+1 if E = 1, s = 1, and d = R
= xi if E = 1, s = 0
= 0 if E = 0 s d yi E 1
xi+1
xi-1 xi
Can be implemented with a mux

24. Shifter Design

25. Barrel Shifter shift x s0 s1 s2 0 1 0 1 0 1 O or 1 shift O or 2 shift
0 1
0 1
0 1 s0
O or 1 shift s1
O or 2 shift
0 1
0 1
0 1
0 1
0 1 s2
O or 4 shift y
0 1
0 1
0 1
0 1
0 1
0 1

26. Shifters as Multipliers and Dividers
A left shift by N bits multiplies a number by 2N
Ex: << 2 = (1 × 22 = 4)
Ex: << 2 = (-3 × 22 = -12)
The arithmetic right shift by N divides a number by 2N
Ex: >>> 2 = (8 ÷ 22 = 2)
Ex: >>> 2 = (-16 ÷ 22 = -4)