1. EEL 3705 / 3705L Digital Logic Design
Fall 2006 Instructor: Dr. Michael Frank Module #8: Modular Combinational Logic (Thanks to Dr. Perry for some slides)
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M. Frank, EEL3705 Digital Logic, Fall 2006

2. M. Frank, EEL3705 Digital Logic, Fall 2006
Wednesday, Jan. 31, 2007
Announcements:
“Perfect Lab #1 Report” example has been posted
go over it
You are doing your Lab #2s this week
Lab #3 assignment will be posted later today
Modular 2-digit display, reusing 1-digit circuit
HW#1 will be posted tonight or tomorrow
Midterm #1 tentatively scheduled for Feb. 12th
Today’s lecture material:
How to group wires in simulator and count through input values
Introduction to modular combinational design
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3. M. Frank, EEL3705 Digital Logic, Fall 2006
Upcoming Schedule
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4. M. Frank, EEL3705 Digital Logic, Fall 2006
Monday, Feb. 5, 2007
Announcements:
Midterm #1 will be 1 week from today
We will have a review session in class this Friday.
A homework assignment (for the lecture course) has been posted on Blackboard
It is to help prepare you for the midterm exam
It is due midnight this Wednesday
Lab #3 is starting Tuesday
Come to my office hours Tu. 2-5 pm if you are stuck!
Today’s Topic:
Continue coverage of common modular components:
Decoders, encoders, multiplexers, demultiplexers…
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5. M. Frank, EEL3705 Digital Logic, Fall 2006
Midterm Exam Coverage
Midterm Exam #1 will cover the following CIOs:
CIO #1. [BinConv] Convert numbers between different number systems (including binary, octal, decimal and hexadecimal).
CIO #3. [BoolCirc] Derive digital circuits from optimized Boolean equations and compute the Boolean equations of a digital circuit.
CIO #5. [K-maps] Use Karnaugh maps to optimize combinational logic, including incompletely specified logic.
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6. M. Frank, EEL3705 Digital Logic, Fall 2006
Upcoming schedule
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M. Frank, EEL3705 Digital Logic, Fall 2006

7. Why K-maps are Rarely Used In Practice
In the real world, combinational functions of significant complexity (more than n=4 or so input bits) are almost never designed as flat, 2-level Sum-of-Products expressions optimized via K-maps.
Some of the reasons are:
The truth tables become large and unweildy (2n rows)
Groupings can’t be easily seen on multi-chart K-maps
Circuit structure becomes large, complex and error-prone
In some cases, even minimal sum-of-products circuits may be exponentially larger (& slower) than alternative designs!
Designers would be constantly “reinventing the wheel”
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M. Frank, EEL3705 Digital Logic, Fall 2006

8. Modular Combinational Design
Rather than using flat AND-OR functions, the preferred, more practical design methodology for any complex combinational component is modular design.
The idea is to create and use libraries of commonly-encountered, reusable modular components, use them as building blocks…
And compose larger, more complex functions out of them.
In a lot of ways, this type of activity has a flavor very similar to software engineering!
This methodology is vastly more efficient in terms of design time, debugging, and understandability and ease of modification of designs.
The resulting designs may not be the most optimal possible, but flat AND-OR designs in many cases would be even less optimal, and would be much harder to maintain!
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M. Frank, EEL3705 Digital Logic, Fall 2006

9. Some Commonly Encountered Modular Combinational Components
The following common elements have a wide variety of uses:
Code conversion, arbitrary functions, etc.:
Decoders
Encoders
Priority encoders
Selection & routing of data:
Multiplexers
Demultiplexers
Lookup tables for arbitrary functions:
ROMs
Integer arith. elements:
Half adders
Full adders
n-bit adders
Ripple-carry adder
Negaters
Subtracters
Comparators
Absolute-value
Multiplers (tend to be slow)
Dividers (tend to be slow)
Floating-point arithmetic elements
Slower, often sequential
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10. … Decoders General form: k-to-2k decoder
Input: A k-bit wide bus encoding a binary number n: nk−1 nk−2 … n2 n1 n0
Output: K=2k bits, e0 … eK−1
Where ei = 1 if and only if n=i
I.e., the propositional meaning of ei is “n is equal to i”
ei thus also corresponds to the ith minterm mi of the input literals e0 e1 e2 e3 n … k
eK-1
When the input is i, output ei = 1, and all other outputs are 0.
We could also draw the output as a bus of K=2k wires.
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11. 2 to 4 Decoder – Truth Table & Boolean Equations1
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12. Some Common Uses of Decoders
Selecting a designated device to activate
Accessing rows/columns of a memory array
Generating minterms to combine with OR gates to implement some arbitrary function
Code conversion (with an encoder)
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13. Example of Using a Decoder to Compute an Arbitrary Function
This is a decimal 7-segment driver
Like you did for lab 2, but not using K-maps
We could further simplify by deleting the “eq8” output, which isn’t used.
Note that the minterms for digit values 0-9 can be shared among all the sum-of-minterms functions that use them, and not recomputed for each one.
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14. M. Frank, EEL3705 Digital Logic, Fall 2006
Encoders
Draw an example 8-to-3 encoder on the board.
Show how to use together with a decoder for code conversion.
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15. Example Encoder Implementation
Any simple encoder can be built just with OR gates… Here’s an 8-to-3 encoder.
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16. Brief aside: Gray codes
To illustrate code conversion, let’s consider an alternative 3-bit binary code for the numbers 0-7.
This one isn’t a radix code!
I.e. individual “bit positions” don’t have values that can be added up to give the value of the number
Instead of the ordinary unsigned base-2 radix expansion of the number, we’ll use a Gray code.
This is a code in which the bit patterns for successive numbers differ in only 1 bit position
We used them already for labeling rows and columns of K-maps; they are also useful for labeling regions of storage media.
A Gray code {gi} for a number can be generated from that number’s radix code {ri} by letting each bit gi of the gray code be given by gi = ri+1ri.
A table of the Gray code generated in this way for 3-bit numbers is shown at right.
Number
3-bit binary representations
Radix 2
Gray
000 1
001 2
010
011 3 4
100
110 5
101
111 6 7
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17. Example of Using an Encoder-Decoder Pair to do Code Conversion
3-bit Binary to Gray-code converter
Between the decoder and encoder, all we need to implement the mapping are wires, connected appropriately!
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18. M. Frank, EEL3705 Digital Logic, Fall 2006
Wed. 2/7/07
Lab 3 this week
HW1 due midnight
Sample exam to be posted
Go over solutions Friday
Midterm on Monday
Lab practicals next week
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19. M. Frank, EEL3705 Digital Logic, Fall 2006
A Simpler Design
Of course, in this case, there is a much simpler implementation of this particular code converter that is based directly on the mathematical definition of the Gray code bits:
This illustrates the general point that it is usually simpler to implement a given non-random function in terms of its mathematical definition, rather than using generic methods.
But, you should still be aware that, if necessary, any arbitrary binary code (even one with a random structure) could be translated to any other using a decoder/encoder pair.
But the method is not very practical for large codeword sizes.
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M. Frank, EEL3705 Digital Logic, Fall 2006

20. Multiplexers (Muxes, Selectors)
A multiplexer selects one of several data input signals to pass through to its output.
It is analogous to a switch/case statement in C.
A multiplexer is defined as follows:
There is an n-bit-wide “select” or “control” input, call it s = sn−1..0.
It is a radix-2 encoding of the index number of the data input line to be selected.
There are N ≤ 2n data input lines, call them d0..dN−1
All the same width as each other – here 1 bit
They are the alternatives we are selecting among
There is one output line, q = ds.
The output is equal to the selected input. d0 d1 … q
dN−1
sn−1..0 n
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21. Building a 4-to-1 Mux from a Decoder
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22. M. Frank, EEL3705 Digital Logic, Fall 2006
Building an Arbitrary Boolean Function (BCD-to-7segment Decoder) Using a MUX
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23. M. Frank, EEL3705 Digital Logic, Fall 2006
Note to Self
There are still way too many slides in the rest of this module!
Need to keep working on making it shorter and more concise
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24. Modular Combinational Logic
Original slides by Dr. Reginald Perry
With modifications & additions by Mike Frank
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25. M. Frank, EEL3705 Digital Logic, Fall 2006
Decoders
General form: n-to-2n decoder
n inputs, 2n outputs
For each input pattern, one and only one output line will be active.
Uses:
“Minterm generator”
Bit/word-line (memory access) circuit
Code conversion
Demultiplexing (routing) of data
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26. M. Frank, EEL3705 Digital Logic, Fall 2006
1-to-2 Decoder
Truth table shown at right
This one can be implemented by just a simple fan-out and an inverter: x y0 y1 1 y0 y0 x x y1 y1
Circuit schematic
Icon
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27. M. Frank, EEL3705 Digital Logic, Fall 2006
Recursive Contruction of n-to-2n Decoder out of 1-to-2 and (n−1)-to-2n−1 Decoders w0
…plus 2n AND gates w1 w2
xn−1..0
xn−1..1
2n−1
2n−1 AND gates …
n−1 2n
2n−1 AND gates z0 x0 z1
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28. 1-to-2, 2-to-4 and 3-to-8 Decoders using recursive design style in Quartus
This is really 4 AND gates in parallel
This is really 8 AND gates in parallel
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29. M. Frank, EEL3705 Digital Logic, Fall 2006
add a slide on the other recursive composition of 2k-to-(2^(2k)) decoders
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30. M. Frank, EEL3705 Digital Logic, Fall 2006
2 to 4 Decoder Equations
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31. M. Frank, EEL3705 Digital Logic, Fall 2006
2 to 4 Decoder: Circuit
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32. 2 to 4 Decoder: Block Symbol
Circuit
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33. 3 to 8 Decoder – Truth Tablex2 x1 x0 y0 y1 y2 y3 y4 y5 y6 y7 1
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34. M. Frank, EEL3705 Digital Logic, Fall 2006
3 to 8 Decoder Equations
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35. M. Frank, EEL3705 Digital Logic, Fall 2006
3 to 8 Decoder: Circuit
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36. 3 to 8 Decoder: Block Symbol
Circuit
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37. M. Frank, EEL3705 Digital Logic, Fall 2006
Design Example
Using only a 3x8 decoder and two-input OR gates, design a logic circuit which implements the following Boolean equation
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38. M. Frank, EEL3705 Digital Logic, Fall 2006
Solution m2 m4 m5
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39. M. Frank, EEL3705 Digital Logic, Fall 2006
2 to 4 Decoder with Enable
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40. M. Frank, EEL3705 Digital Logic, Fall 2006
2x4 Decoder with Enable
Enable is abbreviated as EN
EN is called a Control Signal
Control Signals can be
Active High Signal
EN = 1 – Turns “ON” Decoder
Active Low Signal
EN=0 – Turns “ON” Decoder
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41. 2 x 4 Decoder with Active High Enable – Truth Tabley3 y2 y1 y0 1
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42. 2 to 4 Decoder with Enable Equations
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43. 2 to 4 Decoder with Enable Circuit
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44. 2 to 4 Decoder with Enable Symbol
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45. M. Frank, EEL3705 Digital Logic, Fall 2006
2 x 4 Decoder with Active High Enable – Truth Table (Short hand notation) En x1 x0 y3 y2 y1 y0 d 1
d = don’t care
En has “highest” priority.
If En=0, we “don’t care” about x1 or x0 because Y=0
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46. M. Frank, EEL3705 Digital Logic, Fall 2006
2 x 4 Decoder with Active Low Enable – Truth Table (Short hand notation)
EnL x1 x0 y3 y2 y1 y0 1 d
d = don’t care
En has “highest” priority.
If En=1, we “don’t care” about x1 or x0 because Y=0
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47. 2 to 4 Decoder with Active Low Enable Circuit
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48. M. Frank, EEL3705 Digital Logic, Fall 2006
Design Example
Design a 3x8 decoder using only 2x4 decoders and NOT gates.
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49. M. Frank, EEL3705 Digital Logic, Fall 2006
Solution
“On” when A=0
“On” when A=1
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50. M. Frank, EEL3705 Digital Logic, Fall 2006
Encoders
Opposite of a decoder
2n to n encoder
2n inputs
n outputs
For each input, the circuit will produce an “encoded” output
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51. Example: 4 to 2 Binary Encoder Truth Table1
Assume only one input high at a time!!
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52. M. Frank, EEL3705 Digital Logic, Fall 2006
4 to 2 Encoder Equations
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53. Problems with initial design
Q: How do we tell the difference between an input of all 0’s (i.e. X=0) and X=1?
A: Add another output (IA) that indicates that the input is valid. Let’s make IA active low.
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54. Problems with initial design
If IA = 1 => all lines are 0
If IA = 0 => at least one line is 1
Q: What happens if more than one input is high at the same time?
A: Design a “priority” encoder that will encode the input with the highest priority.
Let’s set X3 with the highest priority, followed by X2, X1, and X0
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55. Example: 4 to 2 Priority Binary Encoder Truth Table1 d
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56. M. Frank, EEL3705 Digital Logic, Fall 2006
Solution 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y1 Y0
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57. 4 to 2 Priority Encoder Equations
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58. Multiplexer/Data Selectors
MUX
Very Important Module!!!
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59. Multiplexer(MUX)/Data Selector
N to 1 multiplexer (or multiplexor)
N=2k data input lines, D0..(N−1)
k=log2(N) control inputs, S(k−1)..0
Binary encoding of index of selected data
One output:
This circuit will “connect” just the selected input to the output.
The selected input is specified by decoding the control inputs.
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60. The Simplest Multiplexer
2-to-1 multiplexer truth table
Output is a copy of
D0 if S0=0
D1 if S0=1 D0 D1 S0 F d 1
Schematic, using 1-to-2 Decoder module
example 2-to-1 MUX Icon
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61. General Construction of a 2k-to-1 MUX from a k-to-2k decoder, ANDs, and an OR
This is just a direct generalization of the schematic on the previous slide. F
“bussed” OR gate 2k 2k 2k
This means 2k AND gates in parallel k
S(k−1)..0
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62. M. Frank, EEL3705 Digital Logic, Fall 2006
Recursive Construction of 2k-to-1 mux from two 2k−1-to-1 muxes (& a 2-to-1 mux)
2k−1
k−1 F 2k
2k−1
Sk−1
S(k−2)..0
k−1
S(k−1)..0 k
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63. 4-to-1 MUX from three 2-to-1 MUXes
Try building some larger sizes for yourself…
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64. Example: 4 to 1 MUX Truth Table
Control
Inputs
Output
Data Inputs D0 D1 D2 D3 S1 S0 F d 1
d = don’t care / Di = data on input i
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65. M. Frank, EEL3705 Digital Logic, Fall 2006
4 to 1 MUX Equation
D’s are the DATA inputs, AB are control inputs and called
the “select” lines.
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66. M. Frank, EEL3705 Digital Logic, Fall 2006
4 to 1 MUX Circuit
Control Inputs
Data Inputs
Output
2x4 Decoder
Only a single AND gate will
be “ON” at a time.
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67. 4 to 1 MUX Symbol Data Inputs Output Control Inputs
A more common, and more mnemonic MUX symbol: D0
Data
Inputs D1 F
Output D2
Control
Inputs
S1..0 D3
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68. Logic with multiplexers
You can implement any n-input logic function with a single 2n-to-1 multiplexer, by feeding appropriate constants into the MUX’s data inputs.
Namely, the list of the function’s output values from its truth table
The multiplexer implements a “lookup table”
it simply looks up the function result from the indicated row of the truth table
Of course, this is generally not the most hardware-efficient way to implement a given function.
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69. MUX Application Example
Using a 4x1 MUX, design a logic circuit which implements:
We have, Y
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70. M. Frank, EEL3705 Digital Logic, Fall 2006
Example
Using a 4x1 MUX, design a logic circuit which implements: a b Y Dn D0 1 D1 D2 D3
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71. M. Frank, EEL3705 Digital Logic, Fall 2006
Solution
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72. Multi-bit Multiplexers
J-bit nx1 mux d0 d1
J bits
deep d2 F
J bits
deep …
dn-1
sel
log2n
j=0 to 3
This is just J separate nx1 multiplexers
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73. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4-bit 4x1 MUX
D0[3..0]
D0[3..0]
D1[3..0]
D1[3..0]
F[3..0]
D2[3..0]
F[3..0]
4 bits deep
D2[3..0]
D3[3..0]
D3[3..0]
A B A B
j=0 to 3
This is just 4 separate 4x1 muxes
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74. M. Frank, EEL3705 Digital Logic, Fall 2006
Example
4-bit 4x1 MUX
Bit 0
Bit 1
Bit 2
Bit 3
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75. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 MUX
For the jth output, we have
D0[j]
D1[j]
D2[j]
F[j]
D3[j] A B
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76. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 MUX
For the bit 0 output, we have
D0[0]
D1[0]
D2[0]
F[0]
D3[0] A B
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77. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 MUX
For the bit 1 output, we have
D0[1]
D1[1]
D2[1]
F[1]
D3[1] A B
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78. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 MUX
For the bit 2 output, we have
D0[2]
D1[2]
D2[2]
F[2]
D3[2] A B
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79. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 MUX
For the bit 3 output, we have
D0[3]
D1[3]
D2[3]
F[3]
D3[3] A B
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80. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 Mux
Complete Circuit
Bit 0
F[0]
Bit 1
F[1]
F[2]
Bit 2
F[3]
Bit 3
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81. M. Frank, EEL3705 Digital Logic, Fall 2006
Example 4 bit 4x1 MUX
Symbol
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82. M. Frank, EEL3705 Digital Logic, Fall 2006
Design Example
Using a 4bit 4x1 MUX, design a 8bit
4x1 MUX
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83. M. Frank, EEL3705 Digital Logic, Fall 2006
Solution
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84. DeMultiplexers/ Data Distributors
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85. Demultiplexer/Data Distributor
Opposite of a multiplexer
1 to N demultiplexer
1 data input
N data outputs
Log2(n) control inputs
This circuit will “connect” a data input to one and only one output. The selected output is specified by a decoding of the control inputs.
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86. Example: 1 to 4 DeMUX Truth TableF0 F1 F2 F3 1
d = don’t care / Di = data on input i
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87. M. Frank, EEL3705 Digital Logic, Fall 2006
1 to 4 DeMUX Equations
D is the DATA inputs, AB are control inputs and called
the “select” lines.
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88. M. Frank, EEL3705 Digital Logic, Fall 2006
1 to 4 DEMUX Circuit
Only one
F will be
active
2x4 Decoder
Only 1 AND gate will
be “ON”
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89. M. Frank, EEL3705 Digital Logic, Fall 2006
1 to 4 DEMUX Symbol
Selected
Lines
Outputs
Data
Input
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90. M. Frank, EEL3705 Digital Logic, Fall 2006
Example
Design a 3x8 decoder using only 2x4 decoders and NOT gates.
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91. M. Frank, EEL3705 Digital Logic, Fall 2006
Solution
“On” when A=0
“On” when A=1
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92. Basic Arithmetic Elements
Half Adder
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93. Half Adder-Truth Table
S=A+B (arithmetic sum) A B S1 S0 1
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94. M. Frank, EEL3705 Digital Logic, Fall 2006
Half Adder Circuit
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95. Full Adder-Truth Table
S=A+B+C (arithmetic sum) A B C S1 S0 1
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96. M. Frank, EEL3705 Digital Logic, Fall 2006
Full Adder
You can show!!!
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97. M. Frank, EEL3705 Digital Logic, Fall 2006
Synthesis
Logic Equation
Logic Circuit
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98. M. Frank, EEL3705 Digital Logic, Fall 2006
Synthesis
Logic Equation
Logic Circuit
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99. Synthesis Full Adder CircuitB
S(0) C
S(1)
S(0)
S(1)
Simulation
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M. Frank, EEL3705 Digital Logic, Fall 2006

100. Full Adder from Two Half Adders
Given bits a,b,c, computes (s1s0)2 = a + b + c.
Can build it using two half adders to compute the low-order bit of the sum as s0 = (a⊕b)⊕c.
Plus an extra OR gate needed to combine the carries.
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

101. M. Frank, EEL3705 Digital Logic, Fall 2006
Ripple Carry Adder
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

102. M. Frank, EEL3705 Digital Logic, Fall 2006
Conceptualization
4-bit adder (worst case) 1 1 1
1111
11110
For the “worst case” we need to add
three bits to generate a single output bit
with a possible carry out.
Can we use our single bit adder for this?
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

103. M. Frank, EEL3705 Digital Logic, Fall 2006
Ripple Carry Adder
We can cascade several full adders to create a ripple carry adder
The circuit gets its name because the carry bit “ripples” from one bit position to the next
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

104. M. Frank, EEL3705 Digital Logic, Fall 2006
Conceptualization
First, let’s look at two bits
A(1)
FullAdder C A B
S(0)
S(1)
B(1)
Sum(1)
A(0)
FullAdder C A B
S(0)
S(1)
B(0)
Sum(0)
What about the carry?
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

105. M. Frank, EEL3705 Digital Logic, Fall 2006
Conceptualization
Let’s connect the two full adders
A(1)
FullAdder C A B
S(0)
S(1)
B(1)
S(1)
Cin
A(0)
Cout
FullAdder C A B
S(0)
S(1)
B(0)
S(0)
Set carry in for first bit to 0. Why?
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

106. M. Frank, EEL3705 Digital Logic, Fall 2006
Analysis
Let’s test this for a few cases:
FullAdder C A B
S(0)
S(1) 00
000
FullAdder C A B
S(0)
S(1)
Correct!!!
Rule of thumb: Always test simple cases first!!
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

107. M. Frank, EEL3705 Digital Logic, Fall 2006
Analysis
Let’s test this for the a few cases 1 1
FullAdder C A B
S(0)
S(1) 1 1 11
110 1 1
FullAdder C A B
S(0)
S(1)
Correct!!!
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

108. M. Frank, EEL3705 Digital Logic, Fall 2006
Analysis
Let’s test this for the a few cases
FullAdder C A B
S(0)
S(1) 1 1 01
010 1 1
FullAdder C A B
S(0)
S(1) 1
Correct!!!
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

109. Four Bit “Ripple” Adder
Carry out
Carry in
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

110. 8-bit Ripple Carry Adder
Use two 4-bit adders
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006

111. 16-bit Ripple Carry Adder
Use two 8-bit adders
11/11/2018
M. Frank, EEL3705 Digital Logic, Fall 2006