1. Chapter 4 Combinational Logic

2. 4.1 Introduction Logic circuit
Combinational circuit
Sequential circuit
Combinational circuits consist of logic gates
Sequential circuits consist of storage elements and logic gates

3. 4.2 Combinational Circuits
A Combinational Circuit
consists of logic gates
its outputs are determined from the present inputs

5. 4.3 Analysis Procedure Step1: Label all gate outputs
Step 2: Label all gate inputs and find the Boolean functions for these gates.
Repeat the step 2 until the outputs of circuit are obtained
Obtain the output Boolean functions in terms of input variables

7. F2 = AB + AC + BC
T1 = A + B + C
T2 = A B C 
T3 = F2’T1
F1 = T3 + T2
F1 = T3 + T2 = F2’T1 + A B C
= (AB + AC + BC)’(A + B + C)
= A’BC’+A’B’C+AB’C’+ABC

8. Truth Table of Figure 4-2

9. 4.4 Design Procedure
1. Determine the required numbers of inputs and outputs and assign a symbol to each
2. Derive the truth table
3. Obtain the simplified Boolean functions
4. Draw the logic diagram and verify the correctness of the design

10. Code Conversion Example (BCD  Excess-3 Code)

13. 4.5 Binary Adder-Subtracter
Carry
Half adder
Full adder
Binary adder
Adder with carry lookahead
Binary adder-subtractor

14. Half adder

16. Full Adder

20. 4-bit Binary adder

21. Carry Propagation

22. Carry Lookahead Generator
Pi = Ai Bi
Gi = Ai Bi
Si = Pi Ci
Ci+1 = Gi + Pi Ci

25. Binary Subtractor

26. Overflow
An overflow
If two numbers added are both positive or both negative
v = c  s (c: carry s: sign)

27. 4.6 Decimal Adder
Calculators that perform arithmetic operations directly in the decimal number system.
Decimal adder
9 inputs
5 outputs

28. BCD Adder

29. BCD Adder(continued)
When the binary sum is greater than 1001 or has an output carry, K, a correction is needed.
The condition for a correction
C = K + Z8Z4+Z8Z2
When C=1, it is necessary to add 0110 to the binary sum.

31. 4.7 Binary Multiplier

32. 4.7 Binary Multiplier(continued)
For J multiplier bits and K multiplicand bits
(J x K) AND gates
(J-1) K-bit adders
A product of (J+K) bits

34. 4.8 Magnitude Comparator
The outcome of comparator is to indicate whether
A>B
A<B
A=B

35. 4.8 Magnitude Comparator (continued)
A = A3 A2 A1 A0
B = B3 B2 B1 B0
Assume that xi = Ai Bi +A’i B’i
(A > B) = A3 B’3 + x3 A2 B’2 + x3 x2 A1 B’1
+ x3 x2 x1 A0 B’0
(A < B) = A’3 B3 + x3 A’2 B2 + x3 x2 A’1 B1
+ x3 x2 x1 A’0 B0

37. 4.9 Decoders
Decoder: to convert binary information from n input lines into a maximum of 2n unique output lines

38. 4.9 Decoders(continued)
A decoder is also used in conjunction with other code converters such as a BCD-to-seven-segment decoder.
The 3-to-8 line decoder circuit
three inputs
eight outputs

40. Decoder with Enable Input

41. Decoder/Demultiplexer
A decoder with enable input can function as a demultiplexer.
Demultiplexer
A circuit that receive information from a single line and direct it to one of 2n possible output lines.
Decoder/demultiplexer
A decoder with enble input

42. How to form a larger decoder circuit

43. Combinational Logic Implementation with a Decoder
A decoder provides the 2n minterm of n input variables.
An example (Refer to Table 4-4)
S(x,y,z) =  (1,2,4,7)
C(x,y,z) =  (3,5,6,7)

44. A Full Adder with a decoder

45. 4.10 Encoders
A digital circuit that performs the inverse operation of decoder.
2n (or fewer) input lines
n output lines
Example: the octal-to-binary encoder
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7

46. Octal-to-Binary Encoder

47. Priority Encoder
A priority encoder is an encoder that includes the priority function.
If two or more inputs are 1 at the same time, the input having the highest priority will take precedence.

48. Priority Encoder

51. 4.11 Multiplexers(MUX)
A combinational circuit that selects binary information from one of many input lines and direct it to a single output line
A selector
Select lines(S)

55. Boolean Function Implementation Using MUX
F(x,y,z)= (1,2,6,7)

56. Boolean Function Implementation Using MUX (continued)
F(A,B,C,D)= (1,3,4,11,12,13,14,15)

58. Three-State(Tri-State) Gates

60. 4.12 HDL for Combinational Circuits
Gate-level modeling
Dataflow modeling
Behavioral modeling

61. Gate-Level Modeling Keywords: and,nand,or,nor,xnor,not,buf x: unknown
z: high impedance
vector: multiple bit width

62. Gate-Level Modeling(continued)

63. HDL Example 4-1

64. Three State Gates
Four types of three state gates

65. An Example module maxtri(A,B,select,OUT) input A,B,select; output OUT;
tri OUT;
bufif1(OUT,A,select);
bufif0(OUT,B,select);
endmodule

67. Dataflow Modeling
Verilog HDL Operators

68. Dataflow Modeling(continuous)
assign: a statement that assign a value to a net.
net: a data type to represent a physical connection between circuit elements

69. Dataflow Modeling(4 bit adder)

70. Dataflow Modeling(4 bit adder)
module binary-adder (A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B + Cin;
endmodule

71. Dataflow Modeling(continued)
- Conditional operator(? : )
condition ? true-expression : false-expression
assign OUT = select ? A : B;

72. Behavioral Modeling
To represent digital circuits as a functional and algorithmic level
It is used mostly to describe sequential circuits
always: followed by a list of procedural assignment statements.
reg: data type to retain a value until a new value is assigned.
repeat: a looping statement

73. A Stimulus Module Form of A Stimulus Module 1. module testname.
2. declare local reg and wire identifiers.
3. instantiate the design module under test.
4. generate stimulus using initial and always statements.
5. display the output response
endmodule

75. System tasks useful for display
$write
$monitor
$time
$finish