1. CMOS Analog Design Using All-Region MOSFET Modeling
Chapter 8
Operational amplifiers
CMOS Analog Design Using All-Region MOSFET Modeling

2. The ideal operational amplifier+ vi -
Avi RS vo
A
RS=0 + vi -
Gmvi GS vo
Gm=AGS
CMOS Analog Design Using All-Region MOSFET Modeling

3. Applications of operational amplifiers - 1+ vi - R2 R1 vo
Inverting amplifier - + R2 R1 vi vo
Non inverting amplifier
CMOS Analog Design Using All-Region MOSFET Modeling

4. Applications of operational amplifiers - 2+ R2 i vo
Transimpedance amplifier
Continuous-time filters
SC filters
D/A & A/D converters
Sensor signal conditioning
Voltage & current references
Comparators
Nonlinear analog functions,
(d) C + vo - R vi
CMOS Analog Design Using All-Region MOSFET Modeling

5. CMOS Analog Design Using All-Region MOSFET Modeling
Applications of operational amplifiers - 3 C + vo - R vi 1 2
S/H circuit C2 + vo - vi C1 1 2
Switched-capacitor integrator
CMOS Analog Design Using All-Region MOSFET Modeling

6. CMOS Analog Design Using All-Region MOSFET Modeling
Performance parameters of op amps - 1
Table 8.1 Measured dc and ac characteristics of the buffered op amp of reference [7].
10 mW
Power dissipation
0.88 V
Vout-
4.12 V
Vout+
1 mV
Offset voltage
18.8 V/s
SR- (50 || 33 pF load)
20.4 V/s
SR+ (50 || 33 pF load)
11.4 MHz
Gain-bandwidth product
67.2 dB
DC gain (163|| 33 pF load)
5 V
Supply voltage
CMOS Analog Design Using All-Region MOSFET Modeling

7. CMOS Analog Design Using All-Region MOSFET Modeling
Performance parameters of op amps - 2
Table 8.2 Experimental performance of the operational amplifiers of [8] (Vsupply = 1 V, Technology: 1.2-m CMOS, C = 15 pF).
56.7 dB
51.5 dB
54.4 dB
52.1 dB
PSRR+
PSRR-
58 dB
62 dB
CMRR
359 nV/Hz
171 nV/Hz
82 nV/Hz
267 nV/Hz
91 nV/Hz
74 nV/Hz
vni 1 kHz)
vni 10 kHz)
vni 1 MHz)
-77 dB
-57 dB
-54 dB
-32 dB
THD (0.5 1 kHz)
THD ( kHz)
0.9 V/s
1.7 V/s
0.8 V/s
1 V/s
SR+
SR-
73o
61o
Phase margin
2.1 MHz
1.9 MHz
Unity-gain frequency
70.5 dB
87 dB
DC gain
208 A
410 A
IDD (supply current)
0.26 mm2
0.81 mm2
Active die area
Amplifier II
Amplifier I
Parameter
CMOS Analog Design Using All-Region MOSFET Modeling

8. CMOS Analog Design Using All-Region MOSFET Modeling
The differential amplifier as an op amp - 1 CL I2 IT
I1= I3 i0 M4 M3 I4 vO +
vG1 - M1 M2
vG2
1:1
VSS
Low gain
Reduced output swing
What is the maximum output swing when the conventional differential pair is used for a buffer?
CMOS Analog Design Using All-Region MOSFET Modeling

9. CMOS Analog Design Using All-Region MOSFET Modeling
The differential amplifier as an op amp - 2
Telescopic-cascode differential amplifier VO M7 M6 +
VG1 -
VDD
VG2 M5 IT M1 M2 VX M3 M4 M8
VBN
VBP
What is the maximum output swing when the telescopic-cascode differential pair is used for a buffer?
CMOS Analog Design Using All-Region MOSFET Modeling

10. CMOS Analog Design Using All-Region MOSFET Modeling
The symmetric op amp - 1
VSS IT +
vG1 - M1 M2 I1 I2
vG2
Current Mirror
B:1 CL
BI1
BI2
Io= B(I2-I1)
1:B
1:1
CMOS Analog Design Using All-Region MOSFET Modeling

11. CMOS Analog Design Using All-Region MOSFET Modeling
The symmetric op amp - 2 VO M1 M2 +
VG1 -
VG2 M4
1:B IT VX M3 M5
VDD M6 M7 M8
B:1
1:1 CL IL VY -1
I1/IT
I2/IT 4 2 -2 -4 1
IL/BIT
VID (a. u.)
CMOS Analog Design Using All-Region MOSFET Modeling

12. CMOS Analog Design Using All-Region MOSFET Modeling
The symmetric op amp - 3
Io= B(I2-I1)
VSS IT +
vG1 - M1 M2 I1 I2
vG2
B:1
1:B
1:1
BI1
BI2 CL
asymmetry
Common-mode input range: see diff. amp.
CL+CP + vo -
Current mirrors delays were neglected
CMOS Analog Design Using All-Region MOSFET Modeling

13. CMOS Analog Design Using All-Region MOSFET Modeling
Problem: VO M7 M6 +
VG1 -
VDD
VG2 M5 IT M1 M2 VX M3 M4 M8
VBN
VBP
Suppose that the high-swing telescopic op amp will be used in an application such that VICM is constant and chosen as equal to the minimum voltage such that ISS remains in saturation. In this case, what would be the maximum output swing when Vb1 and Vb2 are optimally biased?
Telescopic differential amplifier with high-swing cascode current mirror
CMOS Analog Design Using All-Region MOSFET Modeling

14. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 1 IT
IT/2 i
2i M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + - IB
VDD
VSS
Vbias2 vo CL
vi1
vi2
Vbias1 N2 N1
Vbias3
Can be replaced with high-swing current mirror to increase positive output swing
CMOS Analog Design Using All-Region MOSFET Modeling

15. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 2 IT io M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3 vo CL
vi1
vi2
VB2
VB1
VB4
What is the maximum achievable output swing?
The common-mode input range is
VICM,minVSS;
VICM,max=VDD-VDSsat11-VSG1
VDD
IREF
M16
M12
VSS
M13
M14
M15 to
VB1
VB2
VB3
VB4
M17
M18
Bias network
CMOS Analog Design Using All-Region MOSFET Modeling

16. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 3
Offset voltage IT io M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3 vo CL
vi1
vi2
VB2
VB1
VB4
CMOS Analog Design Using All-Region MOSFET Modeling

17. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 4
Note: The output swing can be around -VSS+2VDSsatn to VDD-2VSDsatp for optimized bias. IT io M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3 vo CL
vi1
vi2
VB2
VB1
VB4 Ro
& doublet
CMOS Analog Design Using All-Region MOSFET Modeling

18. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 5
CMRR IT io M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3 vo CL
vi1
vi2
VB2
VB1
VB4
N-well of input transistors to VDD
CMOS Analog Design Using All-Region MOSFET Modeling

19. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 6 IT io M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3 vo CL
vi1
vi2
VB2
VB1
VB4
PSRRvss
CMOS Analog Design Using All-Region MOSFET Modeling

20. CMOS Analog Design Using All-Region MOSFET Modeling
Folded cascode amplifiers - 7 IT io M1 M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3 vo CL
vi1
vi2
VB2
VB1
VB4
Noise
Input-referred noise
CMOS Analog Design Using All-Region MOSFET Modeling

21. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 1
Common-mode input range: see diff. amp.
VDD CL
VSS M4 M3 M1 M2 M8 M5 M7 M6 IT vi + - CC vo
1:1
1:B
1:2B
inv
non inv
Output swing:
For systematic offset  0.
 same offset voltage as diff. amp.
CMOS Analog Design Using All-Region MOSFET Modeling

22. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 2
VDD CL
VSS M4 M3 M1 M2 M5 M7 M6 IT vi + - CC vo
1:B
1:1
1:2B
inv
non inv
voI
goI +
vid -
gmI
CoI vo
goII CL
-gmII
Frequency
compensation
ioI
CMOS Analog Design Using All-Region MOSFET Modeling

23. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 3
Equivalent differential circuit +
vin - RI
gmIvin CI vI
gmIIvI
RII
CII vo CC
For CC0
Poles relatively close  phase margin can be low or even negative !!!
Exercise: Derive the transfer function Ad(s) of the compensated operational amplifier
CMOS Analog Design Using All-Region MOSFET Modeling

24. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 4
voI
goI +
vid -
gmI
CoI vo
goII CL
-gmII
Frequency
compensation
ioI
Frequency
compensation CC
CC=0
CC0
CMOS Analog Design Using All-Region MOSFET Modeling

25. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 5
s-plane j p1 p2
-goI/CoI
-goII/CL z 
Poles for CC=0
Poles for CC0
Pole splitting
CMOS Analog Design Using All-Region MOSFET Modeling

26. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 6
When you design an op amp you must take into account both load and feedback loop.
|AV|dB
goI/CoI u
goII/CL
(a) Uncompensated op amp
 (rad)
-/2 -
log z
-p1
-p2
(b) Compensated op amp PM
CMOS Analog Design Using All-Region MOSFET Modeling

27. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 7
CMOS Analog Design Using All-Region MOSFET Modeling

28. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 8
CMRR: same as in differential amplifier
CMOS Analog Design Using All-Region MOSFET Modeling

29. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 9
Noise
voI
goI
gmI + -
CoI vo
goII CL
-gmII
enII
enI CC
Input-referred noise of the second stage
Noise of 1st stage prevails over that of the 2nd stage except for frequencies approaching u
CMOS Analog Design Using All-Region MOSFET Modeling

30. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 10 M5 VO M1 M2 +
VG1 -
VDD
VG2 IT CL M3 M4 IL
1:1
1:2B CC M6 M7
inv
ninv
VOI IC
BIT
ID6
CMOS Analog Design Using All-Region MOSFET Modeling

31. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 11
Amplitude x frequency limitation due to SR
Amplitude limitation
SR-limited slope
J. Dostál, Operational Amplifiers, 2nd. Ed., Butterworth-Heinemann, Boston, 1993.
CMOS Analog Design Using All-Region MOSFET Modeling

32. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 12 M5 VO M1 M2
VDD IT M3 M4
1:1
1:2B CC M6 M7
BIT IB M8 +1
voI
goI +
vid -
gmI
CoI vo
goII CL
-gmII
ioI CC +1 CL
Elimination of the feed forward effect of CC using a buffer
CMOS Analog Design Using All-Region MOSFET Modeling

33. CMOS Analog Design Using All-Region MOSFET Modeling
Two-stage amplifiers - 13
Nulling resistor
goII
voI
goI +
vid -
gmI
CoI vo CL
-gmII
ioI CC RZ M5 VO M1 M2
VDD IT CL M3 M4
1:1
1:2B CC M6 M7
BIT M8
Bias
CMOS Analog Design Using All-Region MOSFET Modeling

34. CMOS Analog Design Using All-Region MOSFET Modeling
Some comments on op amp design - 1
No general rules
Specs depend on the application: - + - +
CMIR changes (diff. amp. with complementary input pairs can be required)
CMIR =0 - + - +
Capacitive load
RC load
CMOS Analog Design Using All-Region MOSFET Modeling

35. Improved SNR and matching for m>1
Some comments on op amp design - 2
Improved SNR and matching for m>1
Scalable design: - + m mC - +  C
Switched circuits with fsample>>fNyquist - SR is not important but settling time is
CMOS Analog Design Using All-Region MOSFET Modeling

36. CMOS Analog Design Using All-Region MOSFET Modeling
Three-stage amplifiers +
vid -
gmI
gmII vo CL
-gmIII
CmII
CmI
-gmfII
gmfI
3-stage op amp with nested Miller compensation (NMC). The nested transconductance-capacitance compensation (NGCC) amplifier is the NMC + two transconductors (dashed lines).
CMOS Analog Design Using All-Region MOSFET Modeling

37. Rail-to-rail input stages - 1IT M1 M2 M9
M10
M11 + -
VSS
Vbias1
Vbias3
VSDsat11
VSG1
VSD1
VDS9VDSsat9
Problem of the p-channel input differential pair : VICM<VDD
Similarly, for the n-channel input pair : VICM>VSS
How to get a rail-to-rail differential amplifier ?
Combine p- and n-channel input differential pairs
CMOS Analog Design Using All-Region MOSFET Modeling

38. CMOS Analog Design Using All-Region MOSFET Modeling
Rail-to-rail input stages - 2
Combining p- and n-channel input differential pairs
IT1 io M1 M2 M3 M4 M5 M6 M7 M8
M10
VDD
VSS
+vin
-vin
VB2
VB1
IT2 IB M9
Current switches
Rail-to-rail input differential amplifier
Transconductance, noise, and offset voltage are not constant over the input range. The “current switches” block is included to keep the transconductance approximately constant over the input range.
CMOS Analog Design Using All-Region MOSFET Modeling

39. CMOS Analog Design Using All-Region MOSFET Modeling
Class-AB output stages - 1
Class-A amplifiers: poor efficiency and high quiescent power VI
VDD
VSS VO IB IO RL
-RLIB VO
VDD-VDSsat VI
CMOS class-A source follower
(b) voltage transfer curve
CMOS Analog Design Using All-Region MOSFET Modeling

40. CMOS Analog Design Using All-Region MOSFET Modeling
Class-AB output stages - 2
VDD VI
VSS VO IO
(a) M1 M2 VO
VDD-VDssat1 VI
VSS+|VDssat2|
(b)
(b) voltage transfer curve
(a) CMOS class-B source follower
CMOS Analog Design Using All-Region MOSFET Modeling

41. CMOS Analog Design Using All-Region MOSFET Modeling
Class-AB output stages - 3
(a)
VDD
VSS VO IO VI IB M1 M2 M4 M3
1:N VO
VDD-VDSsat1 VI
VSS+|VDSsat2|
(b)
VI0
(a) CMOS class-AB source follower
(b) voltage transfer curve
Problem for low-voltage supply: Output voltage cannot swing close to the supply rails & stacked diodes
CMOS Analog Design Using All-Region MOSFET Modeling

42. CMOS Analog Design Using All-Region MOSFET Modeling
Class-AB output stages - 4
CMOS common-source output stage and push (IP) and pull (IN) currents versus output current.
CMOS Analog Design Using All-Region MOSFET Modeling

43. CMOS Analog Design Using All-Region MOSFET Modeling
Class-AB output stages - 5
Rail-to-rail output stage and bias circuit for class-AB operation
CMOS Analog Design Using All-Region MOSFET Modeling

44. Class-AB output stages - 6
Two-stage op amp with rail-to-rail class-AB output stage
CMOS Analog Design Using All-Region MOSFET Modeling

45. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 1 R2 +
vod - R1
vid
vo1
vo2 t t
vod
Vocm FD SE
Vopp 2: 1
Noise power
SNR
Even-order harm.
No (match)
Yes
CMRR, PSRR
Improved
CMFB circuit No
Area
~2:
FD = Fully-differential
SE = Single-ended
CMOS Analog Design Using All-Region MOSFET Modeling

46. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 2 M1 M2 M6 M3 M4 + -
VDD
VSS
Vbias
vo2
vi1
vi2
vo1 M5
IT/2
 +
M3r
M1r
M5r
Vcm,ref A A1
Example of idealized FD amplifier (transistors assumed to be matched) and bias network employed to set the common-mode output voltage to Vcm,ref.
CMOS Analog Design Using All-Region MOSFET Modeling

47. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 3
VDD IT M1 M2 M5 M3 M4 + -
VSS
Vbias
vo2
vi1
vi2
vo1 
Vcm,ref R A
M1r
M2r
M5r
M3r
M4r
out
Simplified scheme of an FD amplifier. On the right is the low-gain amplifier, a replica of the main amplifier but with diode connected loads.
CMOS Analog Design Using All-Region MOSFET Modeling

48. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 4
VDD
IT/4 M2 M1 M5 M4 M3 - +
Vcm,ref IT
M3/2
vo2
vi1
vi2
vo1 R
Vocm
2M3
VSS CL
M4/2
FD amplifier with resistive CM detector and the error amplifier on the right employed to set the common-mode output voltage to Vcm,ref.
CMOS Analog Design Using All-Region MOSFET Modeling

49. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 5
Vcm,ref
VSS IT
4M1
8M1
2M5
2IT M5 M3 + -
vo2
vi1
vi2
vo1
Vocm
to Vcm,ref (or VSS) R
An FD amplifier where the two CM transconductors are replicas of the DM transconductor
CMOS Analog Design Using All-Region MOSFET Modeling

50. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 6 M1
vi1
2M1
VDD
4M1 M3 + -
vo2
vi2
vo1 IT
VSS
Vcm,ref
2M3
IT/2
IT/4
An FD amplifier employing CM detection based on differential pairs which are replicas of the DM transconductor
CMOS Analog Design Using All-Region MOSFET Modeling

51. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 7
2M4C
VDD IT
M1A
M2A
M5A
M3A
M4A + -
VSS
vo2
vi1
vi2
vo1
Vcm,ref
M5B
IT/2
M6A
M7A
M6B
M7B
2M4B
An FD amplifier using transistors in the triode region to set the common-mode output voltage to Vcm,ref
CMOS Analog Design Using All-Region MOSFET Modeling

52. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 8
Complete schematic of an FD two-stage op amp including the CM control circuit
CMOS Analog Design Using All-Region MOSFET Modeling

53. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 9
Complete schematic of an FD folded-cascode op amp fabricated in 1.75 m CMOS technology
CMOS Analog Design Using All-Region MOSFET Modeling

54. CMOS Analog Design Using All-Region MOSFET Modeling
Fully-differential amplifiers - 10 IT A
4M1
4M2 M3 M4 M5 M6 M7 M8 M9
M10
M11 + -
VDD
VSS
VB3
vo1
vi1
vi2
VB2
VB1
VB4
vo2 B
(a)
IT/2 M1
2M2
M12
Vcm,ref
2M12
IT/4
(b)
ioA
ioB
Simplified schematics of (a) folded-cascode op amp and (b) common-mode feedback circuit
CMOS Analog Design Using All-Region MOSFET Modeling