1. Exam Review of Cache Memories Dec 11, 2001
“The course that gives CMU its Zip!”
Exam Review of Cache Memories Dec 11, 2001
Topics
Cache memory organization
Cache analysis of C code
Sanjit A. Seshia

2. General organization of a cache memory
A cache of size C
contains
S sets
each of which has
E cache blocks
B bytes
Set bits = s = log(S)
Associativity
E = 1 for direct
mapped
Block offset bits = b = log(B)
C = E x S x B
m bits for Addressing
#(tag bits) = t = m – (s+b)

3. Cache Analysis
Problem from Fall 1999 Final Exam (also Homework probs in the textbook)
Therefore,
E = 1
S = 16K = 2^14
Consider the following system:
Direct mapped cache
Cache size, C = 64Kbytes
Block size, B = 4 bytes
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
Assumptions:
sizeof(char) == 1,
sizeof(int) == 4
buffer begins at address 0
Cache is initially empty
All other variables are in registers

4. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
A “write” is a write to a
C variable of a primitive data
type. For pointers, the size
of the target location depends
on the pointer type.
Code is just scanning the
entire array once
for(j=0; j < 640; j++){
for(i=0; i < 480; i++){
buffer[i][j].r = 0;
buffer[i][j].g = 0;
buffer[i][j].b = 0;
buffer[i][j].a = 0; }
What percentage of
writes in this code
will miss?

5. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
……….
buffer j i
for(j=0; j < 640; j++){
for(i=0; i < 480; i++){
buffer[i][j].r = 0;
buffer[i][j].g = 0;
buffer[i][j].b = 0;
buffer[i][j].a = 0; }
What percentage of
writes in this code
will miss?
Cache Block: r g b a
order of access

6. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
……….
buffer j i
for(j=0; j < 640; j++){
for(i=0; i < 480; i++){
buffer[i][j].r = 0; MISS
buffer[i][j].g = 0; HIT
buffer[i][j].b = 0; HIT
buffer[i][j].a = 0; HIT }
What percentage of
writes in this code
will miss?
Cache Block: r g b a
order of access

7. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
……….
buffer j i
for(j=0; j < 640; j++){
for(i=0; i < 480; i++){
buffer[i][j].r = 0; MISS
buffer[i][j].g = 0; HIT
buffer[i][j].b = 0; HIT
buffer[i][j].a = 0; HIT }
What percentage of
writes in this code
will miss?
ANS:
25 % of writes
will miss

8. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
Accesses the array in
Row-major order
cptr = (char *) buffer;
for(; cptr < ((char *) buffer) + 640*480*4; cptr++){
*cptr = 0; }
What percentage of writes in this code will miss?

9. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr; j
………. i
buffer
cptr = (char *) buffer;
for(; cptr < ((char *) buffer) + 640*480*4; cptr++){
*cptr = 0; }
What percentage of writes in this code will miss?
Still 25% (previous analysis still holds)

10. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr;
iptr = (int *) buffer;
for(; iptr < ((int *) buffer) + 640*480; iptr++){
*iptr = 0; }
What percentage of writes in this code will miss?

11. Cache Analysis(contd)
struct pixel {
char r;
char g;
char b;
char a; }
struct pixel buffer[480][640];
register int i, j;
register char *cptr;
register int *iptr; j
“grouped” into
an int
………. i
Same access pattern as cptr case, but ¼ times as many writes!
iptr = (int *) buffer;
for(; iptr < ((int *) buffer) + 640*480; iptr++){
*iptr = 0; }

12. Cache Analysis(contd)
iptr = (int *) buffer;
for(; iptr < ((int *) buffer) + 640*480; iptr++){
*iptr = 0; }
What percentage of writes in this code will miss?
100% of writes will miss

13. Summary For more problems:
See homework problems at the back of Chapter 6
Cache problems on previous exams
These slides will be available on the “lectures”
webpage.