1. Xilinx/Exemplar Logic FPGA Synthesis Solution

2. The Exemplar Advantage Technology Leadership
Goal: To provide a common methodology of powerful, flexible & integrated solutions for high density FPGAs & ASICs
Market Leadership
2x revenue to the closest competition
70% growth yr.-to-yr.
Over 15,000 seats, more than 5000 customers
Pioneered the concept of technology specific optimization for FPGAs

3. The Exemplar Product Line
Galileo FS is an entry level product, sold through Marshall Industries. It features an easy-to-use interface, and includes a tutorial that covers the complete design flow from HDL language entry and usage through synthesis, place and route and simulation, using Galileo FS and Xilinx Alliance Series.
Galileo Extreme adds a number of features, such as hierarchy preservation, timing optimization, static timing analysis, netlist input and a schematic viewer. A solid product for the mainstream designer.
Leonardo is for designs, and designers, that push the envelope. Key differences between Galileo and Leonardo are the ability in Leonardo to control and manipulate the design hierarchy, to run synthesis interactively, and to use TCL scripts to guide the synthesis process.
($3.5K)
($7 - 10K)
($17.5K)

4. Xilinx-Exemplar Alliance Committed Partnership delivers powerful solution!
Increased technical collaboration
Improve Q of R , Xilinx specific optimization, incremental optimization & ease of use
Joint technical publication
Methodology guide for reduced design time
Enhanced support
Cross training and certification program
The Alliance Program is focused on technical collaboration with the goal of device specific optimization and ease of use in specification setting and navigate the tools. For further technical data and methodology guide please visit the respective web sites.

5. Xilinx-Exemplar Advantage Goal: Reduced Design time & Improved QOR
Powerful HDL Based Methodology
Inference(e.g. RAM), links to verification
Proper Design Management
Easy environment setup, hierarchical management
Constraint Based Optimization
maxdly, Clock_cycle,arrival_time
Integration with Xilinx Place & Route tools
via EDIF, SDF
Joint solution provides you with reduced design time and improved QOR, both getting you increased utilization and increased performance. We believe with the current FPGA revolution you have in your hand densities that can help you design very high performance systems and give you the traditional time to market and flexibility of FPGAs.
These advantages are accomplished by providing product features, enhanced algorithms and better integration with Place & Route tools. RAM based inference gives you the technology choice, links to verification completes the HDL solution, superior design manager gives you hierarchical management. Ease of setting constraints and links with P & R via EDIF and SDF makes this a design environment of choice

6. Xilinx Optimization Technology
Generic Optimization
Timing Driven Synthesis
Resource Sharing
Xilinx Optimization
Optimization and Mapping to LUTs
RAM Inference
Modgen for: Multipliers, Adders, Subtractors, Comparators (e.g. Map to Carry logic for arithmetic functions)
TimeSpecs Embedded in EDIF netlist
Automatic global buffer insertion
Automatic GSR Inference
Complex IO Pad Mapping
Slew rate Control
Assign Pad Location
A couple of key points on this slide:
1. Timing is now as critical as area optimization. With faster speed grade devices costing more, being able to have the design run at speed in a slower part has advantages. And devices have enough capacity for the designer’s logic.
Leonardo users can affect timing in many ways, including
changing hierarchical structure
changing datapath implementation with Modgen
adding constraints
using delay-based optimization (option in tools) instead of area-based
doing critical path retiming
passing TimeSpecs through to the Xilinx tools
2. RAM inferencing is available now with the Exemplar tools. This takes a behavioral/RTL description of the RAM module and implements in the target Xilinx device without the user having to explicitely instantiate the RAM module.

7. Xilinx RAM Inference from RTL
I0 : process (we,address,mem,data_in)
begin
if (we = '1') then
mem(conv_integer(address)) <= data_in ;
end if ;
data_out <= mem(conv_integer(address)) ;
end process ;
RAM_DQ :
Synchronous,asynchronous
single-port
RAM_IO :
bi-directional data line
Allows true technology independent RTL. No one else does this. Excellent for targeting multiple technologies without having to rewrite your RTL.
address
data_in we
data_out
RAM 32x8

8. Xilinx Counter Inference from RTL
architecture rtl of pl_counter is
signal count : std_logic_vector (1 downto 0);
begin
count_it : process(clk,reset)
if (reset = '1') then
count <= "00" ;
elsif (clk = '1' and clk'event) then
if (load = ‘1’) then
count <= data_in;
else
count <= count + "01";
end if;
end process ;
data_out <= count;
end RTL ;
The various flavors of counters are supported by the Exemplar tools.
Like RAMs, allows users to specify true technology independent RTL. Old methods required users to hand-instantiate block from vendor library in order to target technology specific counter.

9. Automatic IO Insertion for Xilinx
IBUF & OBUF cells automatically applied to all I/O signals on top-level module
4 BUFGP buffers automatically inserted on clock & high drive signals
Maps to complex Registered I/O’s cells (OUTFF, INFF) when possible

10. Technical Collaboration Better Future Products
Improvements to Q of R
Improvements to Place & Route run times
Addresses serious methodology issues
Simplifies overall design process by integration of place & route tools

11. Incremental Optimization
Incremental ECO Optimization
Incremental Timing Optimization
Synthesis tool can restructure logic, duplicate logic and replace operators
Design Modification capability build into Synthesis tool
Becomes part of repeatable script
Synthesis
Place &
Route
Design Problems
Areas
Timing Violations
Routing Congestion
Netlist
ECO

12. Timing Analysis & Optimization
Timing Analysis based on wire load models
Constraint-Driven
Set constraints from GUI, script or file
Determine Timing Violations
Critical Path Retiming
Also use Modgen & Hierarchy Manipulation to achieve timing improvements 25

13. Error Cross Highlighting
Graphical HDL
Entry
Synthesis
Place and Route
Error Cross
Highlighting
Static Timing
Analysis
Error Highlighting between Synthesis schematics, HDL code and Place & Route

14. Generating Timespec Information
Comb.
Logic Q D
Clock Constraint
Timespec Constraints Generated by Leonardo and Embedded in EDIF Netlist as properties
(instance ix41 (viewRef NETLIST (cellRef OBUF (libraryRef xi4xv ))))
(instance ix29_ix6 (viewRef NETLIST (cellRef FDCE (libraryRef xi4xv )))
(property TNM (string "GROUP_0"))
(property INIT (string "R")))
(instance ix29_ix9 (viewRef NETLIST (cellRef FDCE (libraryRef xi4xv )))
(instance ix51 (viewRef NETLIST (cellRef TIMESPEC (libraryRef xi4xv )))
(property TS1 (string "FROM:GROUP_0:TO:GROUP_0=4.76ns")))
(instance ix50 (viewRef NETLIST (cellRef EQN (libraryRef xi4xv )))
(property EQN (string "((I0*I1)+(~I0*~I1))"))
(property area_add_report (string "1"))
(property area_add_units (string "Packed CLBs")))
Leonardo EDIF Netlist 1

15. Operators Implemented by MODGEN
Module Generation
Hand-crafted Results!
...
Z<= A + B;
Maps directly to target technology
Xilinx specific operators created using CY4 carry chain logic
All arithmetic operators support signed & unsigned arithmetic A
add_32 Z B
Choice
Area
Speed
Runtime
add_32
Arch1
250
21nS 2s
Arch2
390
15nS 3s
Arch3
500
12nS 3s
Arch4
650
6nS 4s
Arch5
920
5nS
11s
FPGA-Specific architectures
FPGA vendor generators
Module Generation is Exemplar’s method for data path synthesis. Modgen infers the behavior from the RTL, and implements a parameterized module for the datapath operator. The implementations are technology specific (by device family) for optimal performance and resource utilization. The module implementations are also parameterized by bus size and by the speed/area tradeoff selected by the user. I.e., for a 14 bit add operation, a 14 bit adder is built; a 16 bit adder is not used.
It should also be noted that VHDL 93 constructs such as shift and rotate are supported by the Exemplar tools, including Modgen.
Operators Implemented by MODGEN 2

16. Leonardo High Control Optimization through Attributes
Preserve Internal Signals and Signalnames
Various attributes may be set too further control the synthesis/optimization process. Preserving signals for downstream use in simulation can be helpful for debugging purposes. Adding clock buffers (done automatically by default) can improve design performance. Not shown here is the ability to restrict buffering of a specified signal, for example a reset, if it exceeds design fanout rules. Other attributes are also available. All these can either be set from the user interface, as shown, or embedded in the source code (VHDL only).
Insert Internal clock Buffers 3

17. Timing Driven Synthesis
Clock Constraint
Clock Period
Multiple Clock Support
Multi-cycle paths
Support for false paths
Input Arrival Delay
Clock to Out Delay
New constraint editor in v5.0
5/98
This is the new constraint editor for Easier to use and more intuitive than either the current Galileo or Leonardo constraint editors.
This constraint editor will allow global constraints such as max delay between input ports and registers, registers and output ports, etc.
However, when more power is needed for setting constraints, users can specify arrival times on a filtered design browser view of input ports, specify false paths, multicylce paths. 4

18. Multi-Pass Optimization
Standard Effort Performs 4 Optimization Passes
Quick Mode Performs 1 Optimization pass Based on Heuristics
Best Results is used
Each Pass Employs different Optimization Groups
A typical design cycle with Exemplar might go as follows:
1. Run synthesis with defaults, including Quick mode optimization, to get utilization/performance estimates.
2. Run synthesis with Standard Effort optimization, letting the tool choose the best results (best optimization pass) for each module in the hierarchy.
3. Run synthesis to tweak the design for timing or area, using only the best optimization passes for each module as determined in Step 2.
Best Pass Automatically Selected for each block of Hierarchical Designs 5

19. Support for Bottom-up Design
Required for Gate Array Designs
Perform optimization on individual blocks and Top-level
No Load constraints on sub-blocks
Must perform top-level opt to insert I/O buffers and Reset circuit
Exemplar’s ability to read in EDIF, and to manipulate hierarchy, provides important flexibility in design flows and methodologies. This flexibility is particularly useful for large designs, and for designs where a team is involved.
LEONARDO {5} read -format edif A.edif B.edif C.edif
LEONARDO {6} read -format vhdl top.vhdl
LEONARDO {6} optimize -ta xi4xv -no_hier -area -chip 6

20. Hierarchy Manipulation
Group
LEONARDO{5} group B C -inst_name BC
Ungroup
Hierarchy manipulation and control is key to success with large, aggressive designs.
A typical design cycle for a large design might go as follows:
1. Group all timing-sensitive modules together under the top level
2. Group all the rest of the modules together
3. Ungroup, or flatten, these two main modules
4. Optimize one module for delay, the other for area
5. Iterate as required to meet design requirements
LEONARDO{6} ungroup B 7

21. State Machine Optimization
Explicit State Machine Encoding (v4.2)
Template Coding Style
Re-encoding on the fly
Implicit State Machine Encoding (v5.0)
Recognizes state machine functionality from any coding style
Supports user defined encoding style
New FSM Optimizations (v5.0)
Dead State Analysis and removal
Unreachable State Analysis and removal 8

22. Summary Overview of current features Future Development
Multipass Optimization
RAM Inference
Hierarchy Management
Module Generation
Future Development
Error Cross Highlighting
Incremental Optimization
Synthesis and Place & Route Integration 33