1. Using FPGAs with Processors in YOUR Designs
Class 3: Tool Support
9/25/2013
Warren Miller

2. This Week’s Agenda
9/23/13 An Intro to FPGAs with Processors 9/24/13 Architecture Details 9/25/13 Tool Support 9/26/13 Application Examples 9/27/13 A Review of YOUR Designs

3. Today’s Topics Goals and Objectives
Understand the tools used with these devices
Software
Intellectual property
Development boards
Tools: General Overview
Microsemi SmartFusion2 Tools
Altera Aria V Tools
Xilinx Zynq Tools

4. Tools Overview All devices have the following tools: Software Hardware
Architecture Specification
Define the target MCU architecture
Processor Code
Write code in “C” or Assembly
FPGA Design
Write code in HDL, IP Cores, etc.
Hardware
Evaluation and Development boards
Documentation, Training, etc.

5. Microsemi System Builder
For the MCU portion of the design
Specify, select and connect required peripherals
Automatically include SmartFusion2 peripheral drivers 
Use familiar IDEs for embedded code development
Create a known-good MCU Subsystem – speed code development
For the FPGA part of the design
Automate key tasks- correct by construction starting point
Instantiate required IP cores from the SmartFusion2 catalog
Hook-up clocks and resets; Initialize peripherals
Populate the software projects with the required firmware
Use established and familiar FPGA tools (Design, Synthesis, Simulation, Debug, etc)
Key Goals:
System Builder is the first stage of an integrated tool flow
Quick learning curve for existing FPGA and MCU designers  
Allow embedded designers to evaluate the processor aspect of the device standalone
Allow FPGA designers to evaluate the FPGA aspect of the device standalone
Allow the two designers to work in parallel on the same device without schedule risk
Produce a “Correct by Construction” base system that dramatically speeds software development
Can be used as is or as a starting point for further customization

6. Guided Development
Asks the user basic questions on system architecture
Covers all elements of the architecture (nothing missed)
Builds on previous answers- defines only needed elements (error proof)
Generates Correct by Construction output when finished
Next use Standard Libero® flow or preferred IDE
Key Device Elements:
Memory
MSS DDR
Fabric DDR
Serial Interfaces
Flash Memory Clients
Memory Element Options:
DDR Memory
DDR2/3 LPDDR
Initialization time
Controller options
Fabric DDR
As above
Embedded Flash
Partitions
The main categories used to group architecture definition tasks within System Builder are listed below:
Key Device Options: Select which memory features will be included in the design- MSS DDR, Fabric DDR, High-Speed Serial Interfaces and Flash Memory Storage Clients.
Memory Options: Define the characteristics of the previously selected memory elements- For MSS External Memory select the type of standard (DDR2, DDR3, LPDDR), the initialization time, and various memory controller configuration options. For Fabric DDR memory make similar selections to the MSS External Memory. For Embedded Flash selections are presented to define the various partitions desired.
Peripheral Options: Define the characteristics of the available peripherals based on previous selections. The detailed definitions are grouped into categories (MSS Master, MSS Peripherals, Fabric Slave and Fabric Master) within which specific peripheral characteristics are selected.
Clock Options: Define the characteristics of the available clock sources based on previous selections. Detailed definitions are selected to configure resources like the FPGA fabric input clock, dedicated clock input, on-chip 1 MHz RC oscillator and external main crystal oscillator.
MCU Options: Define the characteristics for microcontroller options such as the Cortex-M3 processor, cache controller, AHB bus matrix, watchdog timer, real time counter and peripheral DMA controller.
SECDED Options: Define the characteristics for error correction and detection options for the eSRAM, Cache, Ethernet buffers, USB, CAN and DDR buffers. 6

7. Libero® SoC Development Flow
Comprehensive Tool Suite for FPGA Design
SmartDesign design entry
Synplify Pro® synthesis
ModelSim® simulation
Power-driven place-and-route
SmartPower power analysis
SmartTime timing analysis
Flashpro 4 program/debug

8. Design Flow- FPGA
Define Project
Use SmartDesign Canvas
Simulate

9. Libero® SoC Development Flow
Comprehensive Tool Suite for MCU Design
SoftConsole Eclipse-based IDE
GNU C/C++ compiler, GDB Debugger
Free download from Microsemi SoC website
Keil MDK – Microcontroller Development Kit
Combines the ARM C/C++ Compiler
With popular µVision4 debug
IAR Embedded Workbench
First standard compiler for industrial and 8 bit processors

10. Libero® MCU
Define Project with Template
MSS Block Diagram

11. Libero® MCU
Complete Design Entry
Run in SoftConsole

12. Altera Arria V Tool Flow
Extensive eco-system of IP, RTOS, drivers, development boards, partners, etc.
All the ‘Usual Suspects’

13. Arria V Software Details
OpenCL- C-based development for CPU, GPU, DSP and FPGAs
Custom hardware acceleration
Q-sys system-level integration
Automation of IP integration, design reuse, team-based design, etc
SoC EDS (Embedded Design Suite)
ARM Development Studio 5 Altera Edition Toolkit
U-Boot and Linux builds, source and binaries
Altera SoC Boards run right out of the box
Yocto open source Linux build environment
Device driver development, OS porting, Bare-Metal Programming, Linux application development, Multi-core debugging, System debugging

14. Zynq Software Tools

15. Zynq Software Details
Xilinx XPS GUI-driven configuration of Zynq designs
Exports configuration for auto-generation of First Stage Boot-loader, Bare metal BSP and Linux BSP
Software Development Kit (SDK)
Based on Eclipse and CDT
System debugger multi-processor support
Custom libraries and Device drivers
Custom aware design
Integrated debug with HW/SW Cross-triggering and Debug
Software Profiling and Optimization

16. Hardware Kits- Xilinx

17. Hardware Kits- Microsemi SF2

18. Hardware Kits- Altera Cyclone V

19. Additional Resources
Altera Arria Web Page Altera Arria Development Kits Microsemi SmartFusion2 Web Page Microsemi SmartFusion2 Development Kits Xilinx Zynq Web Page Xilinx Zynq Development Kits All Programmable Planet Warren’s CEC Course on Application Specific Programmable Logic Devices

20. This Week’s Agenda
9/23/13 An Intro to FPGAs with Processors 9/24/13 Architecture Details 9/25/13 Tool Support 9/26/13 Application Examples 9/27/13 A Review of YOUR Designs