1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. State Assignment Problem
CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff
Homework 9 is due on Monday

4. Administrative Stuff Homework 10 is out
It is due on Monday Nov 4pm

5. Quick Review

6. The general form of a synchronous sequential circuitW
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock
[ Figure 6.1 from the textbook ]

7. Moore Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

8. Mealy Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

9. Moore Machine
The machine’s current state and current inputs are used to decide which next state to transition into.
The machine’s current state decides the current output.

10. Mealy Machine
The machine’s current state and current inputs are used to decide which next state to transition into.
The machine’s current state and current input values decide the current output.

11. Example #1

12. C: z = 1
Reset
B: z = 0
A: z = 0 w = 1
We need to find both the next state logic and the output logic implied by this machine.
[ Figure 6.3 from the textbook ]

13. Next state Present Output state A B C z w = w = 1 C: z = 1 Reset
B: z = 0
A: z = 0 w = 1
Next state
Present
Output
state z w = w = 1 A B C

14. Next state Present Output state A A B B A C C A C 1 z w = w = 1
Reset
B: z = 0
A: z = 0 w = 1
Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
[ Figure 6.4 from the textbook ]

15. How to represent the States?
One way is to encode each state with a 2-bit binary number
A ~ 00
B ~ 01
C ~ 10

16. How to represent the states?
One way is to encode each state with a 2-bit binary number
A ~ 00
B ~ 01
C ~ 10
How many flip-flops do we need?

17. Let’s use two flip flops to hold the state machine’s state

18. Y y 1 1 Y y 2 2
Clock

19. We will call y1 and y2 the present state variables.
Clock
We will call y1 and y2 the present state variables.
We will call Y1 and Y2 the next state variables.
[ Figure 6.5 from the textbook ]

20. Two zeros on the output JOINTLY represent state A.Y y 1 1 Y y 2 2
Clock
Two zeros on the output JOINTLY represent state A.

21. This flip-flop output pattern represents state B.1 Y y 1 1 Y y 2 2
Clock
This flip-flop output pattern represents state B.

22. This flip-flop output pattern represents state C.Y y 1 1 1 Y y 2 2
Clock
This flip-flop output pattern represents state C.

23. What does this flip-flop output pattern represent?1 Y y 1 1 1 Y y 2 2
Clock
What does this flip-flop output pattern represent?

24. This would be state D, but we don't have one 1 Y y 1 1 1 Y y 2 2
Clock
This would be state D, but we don't have one
in this example. So this is an impossible state.

25. We will call y1 and y2 the present state variables.
Next State Logic
Output Logic z Y y 2 2
Clock
We will call y1 and y2 the present state variables.
We will call Y1 and Y2 the next state variables.
[ Figure 6.5 from the textbook ]

26. We will call y1 and y2 the present state variables.
Q(t+1) = Y2Y1
Q(t) = y2y1 Y y 1 1 w
Next State Logic
Output Logic z Y y 2 2
Clock
We will call y1 and y2 the present state variables.
We will call Y1 and Y2 the next state variables.
[ Figure 6.5 from the textbook ]

27. We need to find logic expressions for Y y 1 1 w
Next State Logic
Output Logic z Y y 2 2
Clock
We need to find logic expressions for
Y1(w, y1, y2), Y2(w, y1, y2), and z(y1, y2).
[ Figure 6.5 from the textbook ]

28. We need to find logic expressions for Y y 1 1 w
Next State Logic
Output Logic z Y y 2 2
Clock
We need to find logic expressions for
Y1(w, y1, y2), Y2(w, y1, y2), and z(y1, y2).
[ Figure 6.5 from the textbook ]

29. Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
Suppose we encoded our states in the same order in which they were labeled:
A ~ 00
B ~ 01
C ~ 10
[ Figure 6.4 from the textbook ]

30. The finite state machine will never reach a state encoded as 11.
Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
Next state
Present
Output
state w = w = 1 z A 00
The finite state machine will never reach a state encoded as 11. B 01 C 10 11
[ Figure 6.6 from the textbook ]

31. Next state Present Output state A A B B A C C A C 1 z w = w = 1w = 1 A A B B A C C A C 1
Present
Next state
state w = 1
Output y Y 2 z A 00 01 B 10 C 11 dd d
We arbitrarily chose these as our state encodings. We could have used others.
[ Figure 6.6 from the textbook ]

32. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1
[ Figure 6.6 from the textbook ]

33. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

34. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

35. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1 d
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

36. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1 d
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

37. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1 d
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

38. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1 d
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

39. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1 d
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

40. Present Next state state w = 1 Output y Y 2 z 00 01 10 11 dd d
Q(t) = y2y1 and Q(t+1) = Y2Y1 w y2 y1 Y2 Y1 1 d
Present
Next state
state w = 1
Output y Y 2 z 00 01 10 11 dd d y2 y1 z 1 d
[ Figure 6.6 from the textbook ]

41. Note that the textbook draws these K-Maps
differently from all previous K-maps
(the least significant bits index the columns,
instead of the most significant bits).
Q(t) = y2y1 and Q(t+1) = Y2Y1 w 00 01 11 10 1 y 2 d
Y 1
Y 2 z w y2 y1 Y2 Y1 1 d y2 y1 z 1 d

42. Don’t care conditions simplify the combinatorial logicw 00 01 11 10 1 y 2 d
Y 1
Y 2 z Y 1 wy y 2 = + z w ( )
Ignoring don't cares
Using don't cares
[ Figure 6.7 from the textbook ]

43. [ Figure 6.8 from the textbook ]

44. Y2= w (y1 + y2)
z = y2
Y1= w y1 y2
[ Figure 6.8 from the textbook ]

45. Lastly, we add a reset signal, which forces the machine back to its start state, which is state 00 in this case.
[ Figure 6.8 from the textbook ]

46. t 1 2 3 4 5 6 7 8 9 10
Clock w y z
[ Figure 6.9 from the textbook ]

47. Summary: Designing a Moore Machine
Obtain the circuit specification.
Derive a state diagram.
Derive the state table.
Decide on a state encoding.
Encode the state table.
Derive the output logic and next-state logic.
Add a reset signal.

48. An Alternative State Encoding For Example #1

49. A Better State Encoding
Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
Suppose we encoded our states another way:
A ~ 00
B ~ 01
C ~ 11

50. Y y 1 1 Y y 2 2
Clock

51. We will call y1 and y2 the present state variables.
Clock
We will call y1 and y2 the present state variables.
We will call Y1 and Y2 the next state variables.
[ Figure 6.5 from the textbook ]

52. Two zeros on the output JOINTLY represent state A.Y y 1 1 Y y 2 2
Clock
Two zeros on the output JOINTLY represent state A.

53. This flip-flop output pattern represents state B.1 Y y 1 1 Y y 2 2
Clock
This flip-flop output pattern represents state B.

54. This flip-flop output pattern represents state C.1 Y y 1 1 1 Y y 2 2
Clock
This flip-flop output pattern represents state C.

55. What does this flip-flop output pattern represent?Y y 1 1 1 Y y 2 2
Clock
What does this flip-flop output pattern represent?

56. This would be state D, but we don't have one Y y 1 1 1 Y y 2 2
Clock
This would be state D, but we don't have one
in this example. So this is an impossible state.

57. A Better State Encoding
Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
Suppose we encoded our states another way:
A ~ 00
B ~ 01
C ~ 11

58. A Better State Encoding
Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
Next state
Present
Output
state w = w = 1
A ~ 00
B ~ 01
C ~ 11 z

59. A Better State Encoding
Next state
Present
Output
state z w = w = 1 A A B B A C C A C 1
Present
Next state
state w = 1
Output y 2 Y z A 00 01 B 11 C 10 dd d

60. Let's Derive the Logic Expressions
Present
Next state
state w = 1
Output y 2 Y z A 00 01 B 11 C 10 dd d
[ Figure 6.16 from the textbook ]

61. Let's Derive the Logic Expressions
Present
Next state
state w = 1
Output y 2 Y z A 00 01 B 11 C 10 dd d
Warning:
This table does not enumerate y2y1, in the standard way, so be careful when filling out the K-Map. w 00 01 11 10 1 y 2 Y2 Y1 w 00 01 11 10 1 y 2 1 y 2 z

62. Let's Derive the Logic Expressions
Present
Next state
state w = 1
Output y 2 Y z A 00 01 B 11 C 10 dd d
Warning:
This table does not enumerate y2y1, in the standard way, so be careful when filling out the K-Map. Y2 Y1 y y y y z y 2 1 2 1 1 w y 2 00 01 11 10 00 01 11 10 1 w d d 1 1 1 1 d 1 1 1 1 d d 1
Y2(w, y2, y1) = wy1
Y1(w, y2, y1) = w
z(y2, y1) = y2

63. Original State Encodings
New State Encodings Y1
Y 1 y y y y 2 1 2 1 w 00 01 11 10 w 00 01 11 10 d d 1 1 d 1 1 1 1 d Y2
Y 2 y y y y 2 1 2 1 w w 00 01 11 10 00 01 11 10 d d 1 1 1 d 1 1 1 d z y z y 1 1 y y 2 1 2 1 1 1 d 1 d 1

64. The New and Improved Circuit DiagramY y 2 2
Y1(w, y2, y1) = w D Q z
Y2(w, y2, y1) = wy1 Q
z(y2, y1) = y2 Y y 1 1 w D Q
Clock Q
Resetn
[ Figure 6.17 from the textbook ]

65. Some may be better than others.
Main Idea
Different state assignments of the same Moore machine generally lead to different circuits.
Some may be better than others.

66. Example #2

67. Register Swap Controller
[ Figure 6.10 from the textbook ]

68. Register Swap Controller
Design a Moore machine control circuit for swapping the contents of registers R1 and R2 by using R3 as a temporary.
[ Figure 6.10 from the textbook ]

69. If an output is not given, then assume that it is 0.
State Diagram D: R 3
out 1 = in
Done , w C: 2 B:
A: No Transfer
Reset
If an output is not given, then assume that it is 0.
[ Figure 6.11 from the textbook ]

70. Animated Register Swap

71. Animated Register Swap
0xFF
0x42
0xC9
These are the original values of the 8-bit registers

72. Animated Register Swap1
0xFF
0x42
0xC9
For clarity, only inputs that are equal to 1 will be shown.

73. Animated Register Swap1
0xFF 1
0x42 1
0xC9

74. Animated Register Swap1
0xFF 1
0x42
0x42 1
0xC9

75. Animated Register Swap1
0xFF 1
0x42 1
0x42

76. Animated Register Swap1 1
0xFF 1
0x42
0x42

77. Animated Register Swap1 1
0xFF 1
0x42
0xFF
0x42

78. Animated Register Swap1 1
0xFF 1
0xFF
0x42

79. Animated Register Swap1 1
0xFF
0xFF 1
0x42

80. Animated Register Swap1 1
0xFF
0xFF
0x42 1
0x42

81. Animated Register Swap1 1
0x42
0xFF 1
0x42

82. Animated Register Swap
0x42
0xFF 1
0x42

83. If an output is not given, then assume that it is 0.
State Diagram D: R 3
out 1 = in
Done , w C: 2 B:
A: No Transfer
Reset
If an output is not given, then assume that it is 0.
[ Figure 6.11 from the textbook ]

84. Some Questions How many flip-flops are we going to use?
How many logic expressions do we need to find?

85. , D: R 3 1 = Done w C: 2 B: A: No Transfer Reset W Z Next State Logic
out 1 = in
Done , w C: 2 B:
A: No Transfer
Reset W Z
Next State Logic
Q(t+1)
Flip-Flop Array
Q(t)
Output Logic
Clock

86. , D: R 3 1 = Done w C: 2 B: A: No Transfer Reset R1out win
Done , w C: 2 B:
A: No Transfer
Reset
R1out w
Next State Logic
Y[1:2]
Flip-Flop Array
y[1:2]
Output Logic
R1in
R2out
R2in
R3out
Clock
R3in
Done

87. Present Next state Outputs state A B C D w = 0 w = 1 , D: R 3 1 = Donein
Done , w C: 2 B:
A: No Transfer
Reset
Present
Next state
Outputs
state A B C D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done

88. Present Next state Outputs state A B C 1 D w = 0 w = 1 , D: R 3 1 =in
Done , w C: 2 B:
A: No Transfer
Reset
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done

89. We will consider three encoding schemes.
As we saw before, we can expect that some state encodings will be better than others.
We will consider three encoding schemes.

90. Encoding #1: A=00, B=01, C=10, D=11 (Uses Two Flip-Flops)

91. State Table State-Assigned Table Present Next state Outputs state A BC 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
Y2Y1
y2y1
[ Figure 6.12 & 6.13 from the textbook ]

92. State Table State Assigned Table Present Next state Outputs state A BC 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
Y2Y1
y2y1
[ Figure 6.12 & 6.13 from the textbook ]

93. State Table State Assigned Table Present Next state Outputs state A BC 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
Y2Y1
y2y1
[ Figure 6.12 & 6.13 from the textbook ]

94. State Table State Assigned Table Present Next state Outputs state A BC 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
Y2Y1
y2y1
[ Figure 6.12 & 6.13 from the textbook ]

95. Let's derive the next-state expressions
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done y2 y1 w Y2 Y1 1
Let's derive the next-state expressions

96. Present Next state state Outputs A 00 1 B 01 10 C 11 D w = 0 w = 11 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done y2 y1 w Y2 Y1 1

97. Present Next state state Outputs A 00 1 B 01 10 C 11 D w 00 01 11 10 11 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

98. 0 0 0 1 1 0 0 1 0 1 0 1 Present Next state state Outputs A 00 1 B 011 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

99. 0 0 0 1 1 0 0 1 0 1 0 1 Present Next state state Outputs A 00 1 B 011 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

100. 0 0 0 1 1 0 0 1 0 1 0 1 Present Next state state Outputs A 00 1 B 011 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

101. Let's derive the output expressions
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done y2 y1
R1out
R1in
R2out 1
Let's derive the output expressions

102. Let's derive the output expressions
Present
Next state
state
Outputs A 00 1 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done y2 y1
R1out
R1in
R2out 1
Let's derive the output expressions
We need to derive only these 3 unique ones

103. Present Next state state Outputs A 00 1 B 01 10 C 11 D w = 0 w = 11 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done y2 y1
R1out
R1in
R2out 1

104. Present Next state state Outputs A 00 1 B 01 10 C 11 D1 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done y2 y1
R1out
R1in
R2out 1
R1out = R2in = y1 y2
R1in = R3out = Done = y1 y2
R2out = R3in = y1 y2

105. Present Next state state Outputs A 00 1 B 01 10 C 11 D w = 0 w = 11 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done

106. y1 y2 y1 y2 y1 y2 Present Next state state Outputs A 00 1 B 01 10 C 111 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done

107. Encoding #2: A=00, B=01, C=11, D=10 (Also Uses Two Flip-Flops)

108. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1
[ Figure 6.12 & 6.18 from the textbook ]

109. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1
[ Figure 6.12 & 6.18 from the textbook ]

110. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1
[ Figure 6.12 & 6.18 from the textbook ]

111. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1
[ Figure 6.12 & 6.18 from the textbook ]

112. Let's derive the next-state expressions
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1 w Y2 Y1 1
Let's derive the next-state expressions

113. Present Next state state Outputs A 00 1 B 01 11 C 10 D R1out R1in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1 w Y2 Y1 1

114. Present Next state state Outputs A 00 1 B 01 11 C 10 D w 00 01 11 10 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

115. 0 1 0 0 1 1 0 0 0 1 1 0 Present Next state state Outputs A 00 1 B 01
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

116. 0 1 0 0 1 1 0 0 0 1 1 0 Present Next state state Outputs A 00 1 B 01
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 w 00 01 11 10 1 y 2 Y

117. 0 1 0 0 1 1 0 0 0 1 1 0 Present Next state state Outputs A 00 1 B 01
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 w 00 01 11 10 1 y 2 Y y2 y1 w Y2 Y1 1 Y 1 wy 2 y + = w 00 01 11 10 1 y 2 Y Y 2 y 1 =

118. Let's derive the output expressions
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1
R1out
R1in
R2out 1
Let's derive the output expressions

119. Let's derive the output expressions Once again, we only need to derive
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1
R1out
R1in
R2out 1
Let's derive the output expressions
Once again, we only need to derive
these three unique ones.

120. Present Next state state Outputs A 00 1 B 01 11 C 10 D A B D C R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1
R1out
R1in
R2out 1 A B D C
Note that C and D are swapped in the truth table
due to the new state encoding that was chosen.

121. Present Next state state Outputs A 00 1 B 01 11 C 10 D A B D C R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1
R1out
R1in
R2out 1 A B D C

122. Present Next state state Outputs A 00 1 B 01 11 C 10 D A
R1out
R1in
R2out
R2in
R3out
R3in
Done
w = 0
w = 1
Present
Next state
state
Outputs A 00 1 B 01 11 C 10 D
Y2Y1
y2y1 y2 y1
R1out
R1in
R2out 1 A
R1out = R2in = y1 y2 B
R1in = R3out = Done = y1 y2 D
R2out = R3in = y1 y2 C

123. Let's Complete the Circuit DiagramY y 2 2 D Q Q Y y 1 1 w D Q
Clock Q
R1out = R2in = y1 y2 Y 1 wy 2 y + =
R1in = R3out = Done = y1 y2 Y 2 y 1 =
R2out = R3in = y1 y2

124. Encoding #3: A=0001, B=0010, C=0100, D=1000 (One-Hot Encoding – Uses Four Flip-Flops)

125. One-Hot State Encoding
So far, we have been encoding states in a way that minimizes the number of flip-flops.
But sometimes we can decrease the complexity of our logic if we encode states more sparsely.

126. Encoding for State A D Q Y 2 1 w
Clock y 3 4 1

127. Encoding for State B D Q Y 2 1 w
Clock y 3 4 1

128. Encoding for State C D Q Y 2 1 w
Clock y 3 4 1

129. Encoding for State D D Q Y 2 1 w
Clock y 3 4 1

130. Register Swap Controller
Present
Next state
Outputs
state
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done A A B B C C 1 1 C D D 1 1 D A A 1 1 1

131. Register Swap Controller
Present
Next state
Outputs
state
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done A A B B C C 1 1 C D D 1 1 D A A 1 1 1
Let’s use four flip-flops and the following
one-hot state encoding scheme:
A = 0001
B = 0010
C = 0100
D = 1000

132. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1
[ Figure 6.12 & 6.21 from the textbook ]

133. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1
[ Figure 6.12 & 6.21 from the textbook ]

134. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1
[ Figure 6.12 & 6.21 from the textbook ]

135. State Table (same as before)
Present
Next state
Outputs
state A B C 1 D
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
State-Assigned Table
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1
[ Figure 6.12 & 6.21 from the textbook ]

136. Let's Derive the Next-State Expressions
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1

137. Let's Derive the Next-State Expressions
Y1(w, y4, y3, y2, y1)
Y2(w, y4, y3, y2, y1)
Y3(w, y4, y3, y2, y1)
Y4(w, y4, y3, y2, y1)
We need to do four 5-variable K-maps!
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1

138. Let's Derive the Next-State Expressions
Y1(w, y4, y3, y2, y1) = wy1 + y4
Y2(w, y4, y3, y2, y1) = wy1
Y3(w, y4, y3, y2, y1) = y2
Y4(w, y4, y3, y2, y1) = y3
Or we can be smarter than that 
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1

139. Let's Derive the Output Expressions
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1

140. Let's Derive the Output Expressions
R1out(y4, y3, y2, y1)
R1in (y4, y3, y2, y1)
R2out(y4, y3, y2, y1)
R2in (y4, y3, y2, y1)
R3out(y4, y3, y2, y1)
R3in (y4, y3, y2, y1)
Done(y4, y3, y2, y1)
We need to do seven 4-variable K-maps!
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1

141. Let's Derive the Output Expressions
R1out(y4, y3, y2, y1) = y3
R1in (y4, y3, y2, y1) = y4
R2out(y4, y3, y2, y1) = y2
R2in (y4, y3, y2, y1) = y3
R3out(y4, y3, y2, y1) = y4
R3in (y4, y3, y2, y1) = y2
Done(y4, y3, y2, y1) = y4
Or we can be smarter than that by exploiting the one-hot property
Present
Next State
State
Outputs A
001
0001
0010 B
010
0100 1 C
100
1000 D
000
w = 0
w = 1
R1out
R1in
R2out
R2in
R3out
R3in
Done
y4y3y2y1
Y4Y3Y2Y1

142. Let's Complete the Circuit Diagram
R1out = R2in = y3
R2out = R3in = y2
R1in = R3out = Done = y4 D Q Y 2 1 w
Clock y 3 4
Y1 = w y1 + y4
Y2 = w y1
Y3 = y2
Y4 = y3

143. Questions?

144. THE END