1. CPEG 505
Advanced Logic Design

2. Electronic Circuits
Analog Signals:Have a continuous range of values within some specified limits and can be associated with continuous physical phenomena.
Digital Signals:Typically assume only two discrete values (states) and are appropriate for any phenomena involving counting or integer numbers.

3. BOOLEAN ALGEBRA Boolean Values : ‘0’ / LOW / FALSE ‘1’ / HIGH / TRUE
Boolean Variables can assume any one of ‘0’ or ‘1’ value at a time.
NOT Inversion or Complementation.
AND Logical ‘AND’ operation.
OR Logical ‘OR’ operation.
ExOR ‘Exclusive OR’ operation.
NAND Complement of ‘AND’
NOR Complement of ‘OR’
ExNOR Complement of ExOR

4. C = A.B
ABar = /A
D = A + B

5. E = A xor B
H = A xnor B

6. A A X Y B B
NOR NAND
X = NOT (A+B) = NOT A. NOT B Y = NOT (A.B) = NOT A + NOT B
Inputs Output Inputs Output
A B X A B Y

7. De Morgans Theorems NOT(A+B) = ( NOT A) . ( NOT B)
“The complement of the SUM (OR) of two boolean variables is equivalent to the PRODUCT ( AND)of the complements of the two variables. ”
NOT(A.B) = ( NOT A) + ( NOT B)
“The complement of the PRODUCT (AND) of two boolean variables is equivalent to the SUM(OR) of the complements of the two variables .”

8. DUALITY PRINCIPLE
The important property of Boolean algebra. If the dual of the expression is desired,we simply interchange OR and AND operators and replace 1’s by Ø’s and Ø’s by 1’s.
3-input Combination block

9. Boolean Equation for 3-input Combination block
Sum-of-products for active high logic
PQR + PQR + PQR + PQR = 1
Sum-of-products for active low logic
PQR + PQR + PQR + PQR = 0
Applying Duality principle
(P+Q+R)(P+Q+R)(P+Q+R) (P+Q+R) = 1

10. Implementation of SOP using the array of AND-OR gates

11. Implementation of POS using the array of OR- AND gates

12. Combinational Logic Design: BCD to 7-Segment Decoder
How does a seven segment display work ?
Function of the circuit is to convert a given BCD number from 0 to 9 in to equivalent seven-segment code to drive the display.

13. Active High Logic and Common Cathode 7-segment display
BCD
D3 D2 D1 D0 L

14. Other combinatorial logic blocks

15. MULTIPLEXER 4 TO 1 MUX z Z = S1S0 I0 + S1S0 I1 + S1S0 I2 + S1S0 I3 I0
S1 S0 H = HIGH Voltage level, X =Don’t care
L = LOW Voltage level

16. DECODER 1 of 4 decoder Inputs Outputs EN A1 A0 O0 O1 O2 O3
H X X L L L L L L L H L L L L L H L H L L L H L L L H L L H H L L L H
O0 = A1 A0 EN O2 = A1 A0 EN
O1= A1 A0 EN O3 = A1 A0 EN O0 O1 O2 O3 EN A1 A0

17. PARITY GENERATOR
EVEN B6 B5 B4
B ODD B2 B1 B0

18. PRIORITY ENCODER 1 D 2 C 3 9-LINE B 4 TO A 5 4-LINE 6 PRIORITY8 9

19. MAGNITUDE COMPARATOR OA>B OA=B OA<B A3-A0 B3-B0 4-BIT MAGNITUDE

20. Logic families 1. Classical +5 V logic family
TTL, Schottky TTL, LSTTL, ASTTL, ALSTTL,etc.
2. Classical CMOS family operates with +5 V and above
3. TTL like CMOS family
HC - Series, HCT - Series
V TTL and CMOS logic families
LV TTL, ACT - Series

21. What are 0 and 1 in a Digital circuit ?
Logic family typical I / O Characteristic
VOHmin
VOut
VOLmax
VILmax VIHmin
Gate operated in this
region gives
unpredictable results
Active region:
Gate works like
an amplifier and
not a switch
VIn

22. If two gates of similar or dissimilar logic families are interconnected, the following conditions should be met for proper operation.
G G2
G1 - VOLmax < G2 - VILmax
G1 - VOHmin > G2 - VIHmin
Noise margin
VILmax - VOLmax = logic ‘0’ noise margin
VOHmin - VIHmin = logic ‘1’ noise margin

23. The output of a logic gate can drive inputs of how many gates?
Fan out / Loading
The output of a logic gate can drive inputs of how many gates?
N = ? 1 2 N

24. Sinks current into the input from driver when input is high
High output
IIH
Sources current into the driver when input is low
Low output
IIL
Input Output
Low
( IIL ) Sources Sinks Current
current to driver from load ( IOL )
High
( IIH ) Draws Sources Current
current from driver to the load ( IOH )

25. Conditions for gates to work properly is IOLmax > 1n IILmax
IOHmax > 1m IIHmax
The minimum of [m,n] is the fan-out of the gate
or the number of gates it can drive.

26. DC / AC Characteristics
Characteristics like VOH , VOL , VIH and VIL are called DC Characteristics.
One more important feature is Propagation delay or A C Characteristics.
Input Output

27. Input
Time
Output
Output high to low propagation delay ( tpdhl )
Output low to high propagation delay ( tpdlh )

28. How to choose a logic family?
Speed of operation
Power supply constraints (operating voltage)
Compactness requirements
Cost
Overall power consumption
Interface requirements

29. Today’s need is generally:
Low cost
High speed
Low voltage operation
Low power consumption
Compactness
Easy interface

30. SEQUENTIAL CIRCUITS
Combinational circuits by themselves can do simple jobs viz. add, multiply, divide, multiplex, decode, encode.
Not adequate to implement complete digital system because they don’t have memory.
Sequential circuit bring-in this storage element called Flip-flop

31. What is a Clock?
The functions to be performed by digital system can be broken into a sequence of micro-operations.
Mostly these micro-operations are performed by combinational circuits.
The result of one micro-operation would be required as inputs to next micro-operation.
A group of flip-flops are used to hold these intermediate results.
Clock is used to time each of these micro-operations.
Clock basically defines, the time in which a micro-operation has to be performed. This is called Clock period
If a function of the system needs n micro-operations, the time taken by the system to perform that function is n clock periods.

32. Simplified model of a Digital System
Inputs
Outputs Clock
Flip-flops
Combinational
circuits

33. Parity checking on serial communication line
Data-in Z
Clock
Baud-rate
Data-in
Note: This is not a full parity circuit. Lot of additional circuitry has to be added to make it a proper parity circuit. But it illustrates the idea of digital system using flip-flops & combinational logic.
D Q
QBAR

34. Flip-flops The D flip-flop samples the input at every clock edge
Clock Clock
Positive edge Triggered D Flip-flop Negative edge Triggered D Flip-flop
The D flip-flop samples the input at every clock edge
and holds it at the output till the next clock edge occurs.
D Q
QBAR
D Q
QBAR

35. Rising Edge ( Leading edge or Positive edge): 1
Rising edge
Falling edge
One clock cycle ( Clock Period is the time taken for one clock cycle. )
Rising Edge ( Leading edge or Positive edge):
Clock transition from 0 to 1.
Falling Edge ( Trailing edge or Negative edge):
Clock transition from 1 to 0.
Frequency of Operation= 1 / Clock period

36. D Flip-flop (Rising edge triggered)
Clock
Input
Output
Notice how this portion of the input which is not synchronized to clock edge is ignored.

37. D Flip-flop (Falling edge triggered)
Clock
Input
Output
Notice how this pulse which is synchronized to clock edge has been stretched

38. D Flip-flop Truth table
tn tn+1
D Q tn = time before the active edge of the clock
H H tn+1 = time after the active edge of the clock
L L

39. SUMMARY
1. D flip-flop may work with either positive edge of the clock or negative edge of the clock but never with both.
2. Time between two consecutive rising edges or falling edges of the clock is called clock period, or clock interval or bit time.
3. The D flip-flop samples the logic level at its active edge and holds this level at its output until the next corresponding edge occurs.
4. In effect it is remembering the current input till the next input comes in. That’s why it is called as a memory element of 1-bit.
5. Sequential circuits are made up of a number of flip-flops which sample their inputs at the active edges of clock and hold them till next active edge
6. As a consequence, the output logic levels of all circuits in the system should be stable and valid around clock edges
7. Logic level changes (transitions) occurring on inputs of flip-flops away from clock edges are generally ignored.

40. Other types of Flip-flops
Clock Clock Clock
Clock Clock Clock
S R Flip-flop J K Flip-flop T Flip-flop
S Q
R QBAR
J Q
K QBAR
T Q
QBAR
J Q
K QBAR
S Q
R QBAR
T Q
QBAR

41. State table for Flip-flops
J K QN QN+1 S R QN QN+1 T QN QN D QN QN+1
0 0 QN QN QN QN x QN x 0
x x x /QN x 1
x x 1
1 1 QN /QN invalid

42. Implementation of other flip-flops using D flip-flop
T T Flip-flop
Clock I0
‘0’ I1
‘1’ I2 Y I3
J-K Flip-flop J K
D Q
QBAR
D Q
QBAR

43. Synchronous operation
We’ve seen that the outputs of the flip-flop change at the active edge of the clock. This is called Synchronous operation.
In a fully synchronous digital system all flip-flops operate at the same clock edge and the state of the system changes only at the clock edge.
In modern digital systems it is desirable to do full synchronous design.

44. Asynchronous clear and Asynchronous preset
Often flip-flops are equipped with either
a asynchronous clear or asynchronous preset input.
Clear
Data-in
Clock
Preset
Clr
D Q
QBAR Pr

45. Operation of asynchronous clear and asynchronous preset
Clock
Data-in
Clear
Preset
Output

46. Asynchronous inputs operate immediately without waiting for the clock edge.
Asynchronous Clear changes state of the output to ‘0’ irrespective of D-input or the state of the clock.
Asynchronous Preset changes state of the output to ‘1’ irrespective of D-input or the state of the clock.
Many flip-flops are equipped with only clear or preset.
Some flip-flops have both preset and clear inputs. Such flip-flops are normally equipped with both Q and QBAR outputs.
When both preset and clear are simultaneously activated, both Q and QBAR become logic ‘1’ in such flip-flops. Eg. 74LS74

47. As we see the above flip-flop clears (goes to logic ‘0’) or sets (goes to logic ‘1’) when clear is logic ‘0’ or preset is logic ‘0’.
Such operation is called level sensitive operation, in contrast to clock input which is edge sensitive.
The output of the flip-flop stays in ‘0’ state (or ‘1’ state) as long as clear (or preset) is ‘0’.
Further, the clear and preset signals are effective on the output when they are logic ‘0’ and have no effect when they are logic ‘1’. These kind of signals are called ACTIVE LOW SIGNALS
It is a good design practice to avoid using asynchronous clears and presets unless it is absolutely necessary.

48. Set-up time, Hold time and Frequency of operation
Clock
Input
Output
How narrow can this pulse be to produce the output shown?
When we can not guarantee that the output will appear as indicated?

49. tSETUP Clock tHOLD tSETUP : The minimum amount of time the D-input
should not change before the clock edge occurs
tHOLD : The minimum amount of time the D-input
should not change after the clock edge occurs
Minimum pulse width = tSETUPmin + tHOLDmin

50. Frequency of operation
How fast the clock can be for reliable operation? Or
How small can the clock period be for reliable operation?
For the case of single flip-flop,
FrequencyMAX (fMAX) = 1 / (tSETUPmin + tHOLDmin)
Clock periodMIN = tSETUPmin + tHOLDmin
However, a digital system is not a single flip-flop.
It is a combination of Combinational logic
and flip-flops as shown next.

51. General model of a sequential system
The delay of such a system is governed by delays
through D flip-flops and associated combinational logic

52. Let us consider the following JK flip-flop
‘1’ I2 Y I3
Clock
J K
For the combination of J=K= 1, the flip-flop has to toggle every clock
Output
D Q
QBAR

53. Let tINV = worst case propagation delay of inverter tMUX = worst case propagation delay of multiplexer tD = worst case propagation delay of D flip-flop tS = Set-up time of D flip-flop tH = Hold time of D flip-flop QD = Output of D flip-flop QI = Output of Inverter QM = Output of multiplexer

54. Let us examine various signals (J=1, K=1)
Clock T T T T3
QD tD
QI tINV
QM tMUX
Valid predictable state change will occur at T1 raising edge if
tclk  tSmin + tD + tINV + tMUX
(tclk)min = tSmin + tDmax + tINVmax + tMUXmax
fmax = 1/ (tclk)min

55. Summary
In order for a digital system to work properly, the set-up time and hold time at the input of all flip-flops in the system must be satisfied under all conditions
The maximum frequency of operation is governed by the worst case path delay of the combinational logic, before a flip-flop and the set-up, hold and propagation delays of the flip-flop.

56. Common sequential circuits used in Digital systems
COUNTERS (e g. - Instruction pointer, DMA address counter)
REGISTERS (Registers of CPU, Accumulator, Stack pointer)
SHIFT REGISTERS (Used for logical and arithmetic like multiply / divide)

57. Registers - collection of D flip-flops with a common Enable signals
Enable Data-in
Enable
D Q
D Q Clock
D Q If En = 1 then D  Q
tn tn+1
D Q En D Q
D Q 0 X QN
Clock 1 H H
1 L L
D Q
QBAR

58. Shift Registers Types are used as Parallel to Serial converters
Serial to Parallel converters
Delay elements
Logical and arithmetic operations
Types
Shift right type with serial-in, Parallel out
Shift left type with serial-in, Parallel out
Shift left/right types with serial-in, Parallel out
Universal shift registers, which can be parallelly loaded, shifted left or right.

59. Universal shift register (8-bits)
Parallel Inputs
Clock
Shift right D7 D6 D5 D4 D3 D2 D1 D0 Shift left
serial input serial input
Mode control Parallel Outputs

60. Parallel loading of a register
8-bit data input
Load B7 B6 B5 B4 B3 B2 B1 B Clock
Enable
8-bit data output

61. Shift left operation ‘0’ B7 B6 B5 B4 B3 B2 B1 B0 0 Clock
Shift left B7 B6 B5 B4 B3 B2 B1 B Clock
Enable
‘0’
B7 B6 B5 B4 B3 B2 B1 B Clock

62. Shift right operation ‘0’ 0 B7 B6 B5 B4 B3 B2 B1 B0 Clock
Shift right B7 B6 B5 B4 B3 B2 B1 B Clock
Enable
‘0’
0 B7 B6 B5 B4 B3 B2 B B0
Clock

63. Shift left is equal to multiply by 2!
A7 - A0 = = 36H (54D)
Shift left by 2 positions
Note how the value gets multiplied by 4.
A7 - A0 = = D8H (216D)
Bits thrown out Inserted-in Zeros

64. Shift right is equal to divide by 2!
A7 - A0 = = 36H (54D)
Shift right by 2 positions
Note how the value gets divided by 4.
A7 - A0 = = 0DH (13D)
Inserted-in Zeros Bits thrown out

65. Rotate Left Rotate left B7 B6 B5 B4 B3 B2 B1 B0 Clock Enable

66. Rotate Right Rotate right B7 B6 B5 B4 B3 B2 B1 B0 Clock Enable

67. Ripple counter - 3 bit Up count
PRESENT STATE NEXT STATE
‘1’ QC QC QB QA QC QB QA
‘1’ QB
‘1’ QA
Clock
T Q
QBAR O
T Q
QBAR O
T Q
QBAR O

68. Synchronous counter - 4 bit Up count
PRESENT STATE NEXT STATE FLIP-FLOP INPUTS
D C B A Q3 Q2 Q1 Q D3 D2 D1 D0

69. Synchronous counter - 4 bit Up count
Q Q Q Q0
D D D D0
Clock
D Q
D Q
D Q
D Q
Combinational
block

70. Synchronous counter - 4 bit Up count
Clock Q0 Q1 Q2 Q3