1. COMPUTER DESIGN CENG-212 Dr. Ceyhun ÇELİK celik.ceyhun@gmail.com
Computer Engineering
Gazi University
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2. Chapter 4
The Processor

3. 1. Introduction
Chapter 1 explains that the performance of a computer is determined by three key factors: instruction count, clock cycle time, and clock cycles per instruction (CPI).
Chapter 2 explains that the compiler and the instruction set architecture determine the instruction count required for a given program.
We will see that the implementation of the processor determines both the clock cycle time and the number of clock cycles per instruction in this chapter.
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4. 1. Introduction A subset of the core MIPS instruction set includes:
The memory-reference instructions load word (lw) and store word (sw)
The arithmetic-logical instructions add, sub, AND, OR, and slt
The instructions branch equal (beq) and jump (j), which we add last
shift , multiply, divide and all floating-point instructions are missing.
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5. 1. Introduction
For every instruction, the first two steps are identical:
Send the program counter (PC) to the memory that contains the code and fetch the instruction from that memory.
Read one or two registers, using fields of the instruction to select the registers to read. For the load word instruction, we need to read only one register, but most other instructions require reading two registers.
Three instruction class:
Memory-reference
Arithmetic-logical
Branches
are largely the same. The simplicity and regularity!
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6. 1. Introduction
All instruction classes, except jump, use the arithmetic-logical unit (ALU) after reading the registers.
The memory-reference instructions use the ALU for an address calculation,
the arithmetic-logical instructions for the operation execution,
branches for comparison.
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7. 1. Introduction
After using the ALU, the actions required to complete various instruction classes differ.
A memory-reference instruction will need to access the memory either to read data for a load or write data for a store.
An arithmetic-logical or load instruction must write the data from the ALU or memory back into a register.
For a branch instruction, we may need to change the next instruction address based on the comparison; otherwise, the PC should be incremented by 4 to get the address of the next instruction.
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8. 1. Introduction
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9. 1. Introduction
In practice, these data lines cannot simply be wired together;
we must add a logic element that chooses from among the multiple sources and steers one of those sources to its destination.
multiplexor or data selector
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10. 1. Introduction
Several of the units must be controlled depending on the type of instruction.
The data memory must read on a load and written on a store.
The register file must be written only on a load or an arithmetic-logical instruction.
And, of course, the ALU must perform one of several operations.
So we need three multiplexer and a control unit.
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11. 1. Introduction
A control unit, which has the instruction as an input, is used to determine how to set the control lines for the functional units and two of the multiplexors.
The third multiplexor, which determines whether PC + 4 or the branch destination address is written into the PC, is set based on the Zero output of the ALU, which is used to perform the comparison of a beq instruction.
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12. 1. Introduction
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13. (The regularity and simplicity of the MIPS instruction set)
1. Introduction
A simple decoding process can be used to determine how to set the control lines.
(The regularity and simplicity of the MIPS instruction set)
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14. 2. Logic Design Conventions
The datapath elements in the MIPS implementation consist of two different types of logic elements:
elements that operate on data values, combinational element (such as AND gate or an ALU)
elements that contain state, state element, (such as a register or a memory).
Combinational elements always produce the same output, because they have no internal storage.
State elements completely characterize the computer.
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15. 2. Logic Design Conventions
A state element has at least two inputs and one output. (D-type flip-flop).
The required inputs are the data value to be written into the element and the clock, (which determines when the data value is written).
The output from a state element provides the value that was written in an earlier clock cycle.
Logic components that contain state are also called sequential, because their outputs depend on both their inputs and the contents of the internal state.
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16. 2. Logic Design Conventions
clocking methodology: The approach used to determine when data is valid and stable relative to the clock.
edge-triggered clocking: A clocking scheme in which all state changes occur on a clock edge.
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17. 2. Logic Design Conventions
All signals must propagate from state element 1, through the combinational logic, and to state element 2 in the time of one clock cycle.
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18. 2. Logic Design Conventions
control signal: A signal used for multiplexor selection or for directing the operation of a functional unit.
Control signal contrasts with a data signal, which contains information that is operated on by a functional unit.
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19. 2. Logic Design Conventions
If a state element is not updated on every clock, then an explicit write control signal is required.
Both the clock signal and the write control signal are inputs, and the state element is changed only when the write control signal is asserted and a clock edge occurs.
Asserted: The signal is logically high or true.
Deasserted: The signal is logically low or false.
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20. 2. Logic Design Conventions
An edge-triggered methodology allows us to read the contents of a register, send the value through some combinational logic, and write that register in the same clock cycle.
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21. 2. Logic Design Conventions
For the 32-bit MIPS architecture, nearly all of these state and logic elements will have inputs and outputs that are 32 bits wide, since that is the width of most of the data handled by the processor.
The figures will indicate buses, which are signals wider than 1 bit, with thicker lines.
We may want to obtain a 32-bit bus by combining two 16-bit buses. In such cases, labels on the bus lines will make it clear that we are concatenating buses to form a wider bus.
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22. 2. Logic Design Conventions
IF a 32-bit bus is obtained by combining two 16-bit buses.
In such cases, labels on the bus lines will make it clear that we are concatenating buses to form a wider bus.
The Blue Color indicates a control signal as opposed to a signal that carries data.
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23. 3. Building a Datapath
datapath element: A unit used to operate on or hold data within a processor.
Instruction memory: a memory unit to store the instructions of a program and supply instructions given an address.
program counter (PC): The register containing the address of the instruction in the program being executed.
adder: increment the PC to the address of the next instruction. This adder, which is combinational, can be built from the ALU.
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24. 3. Building a Datapath
To execute any instruction, we must start by fetching the instruction from memory.
To prepare for executing the next instruction, we must also increment the program counter so that it points at the next instruction, 4 bytes later.
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25. 3. Building a Datapath
To execute any instruction, we must start by fetching the instruction from memory.
To prepare for executing the next instruction, we must also increment the program counter so that it points at the next instruction, 4 bytes later.
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26. 3. Building a Datapath
register file: A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.
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27. 3. Building a Datapath lw $t1,offset_value($t2)
sw $t1,offset_value($t2)
sign-extend: To increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item.
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28. 3. Building a Datapath beq $t1,$t2,offset
branch target address: The address specified in a branch.
In the MIPS architecture the branch target is given by the sum of the offset field of the instruction and the address of the instruction following the branch.
We must compute the branch target address by adding the sign-extended offset field of the instruction to the PC.
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29. 3. Building a Datapath
The instruction set architecture specifies that the base for the branch address calculation is the address of the instruction following the branch.
Since we compute PC + 4 (the address of the next instruction) in the instruction fetch datapath, it is easy to use this value as the base for computing the branch target address.
The architecture also states that the offset field is shifted left 2 bits so that it is a word offset; this shift increases the effective range of the offset field by a factor of 4.
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30. 3. Building a Datapath
As well as computing the branch target address, we must also determine whether the next instruction is the instruction that follows sequentially or the instruction at the branch target address.
When the condition is true, the branch target address becomes the new PC, (branch taken)
If the operands are not equal, the incremented PC should replace the current PC, (branch not taken)
The jump instruction operates by replacing the lower 28 bits of the PC with the lower 26 bits of the instruction shifted left by 2 bits. Simply concatenating 00 to the jump off set accomplishes this shift , as described in Chapter 2.
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31. 3. Building a Datapath
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32. 3. Building a Datapath
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33. 3. Building a Datapath
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34. 3. Building a Datapath
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35. 4. A Simple Implementation Scheme
This simple implementation covers
load word (lw),
store word (sw),
branch equal (beq),
the arithmetic-logical instructions (add, sub, AND, OR)
set on less than (slt).
We will later enhance the design to include a jump instruction (j)
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36. 4. A Simple Implementation Scheme
For load word and store word instructions, we use the ALU to compute the memory address by addition.
For the R-type instructions, the ALU needs to perform one of the five actions (AND, OR, subtract, add, or set on less than)
For branch equal, the ALU must perform a subtraction.
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37. 4. A Simple Implementation Scheme
We can generate the 4-bit ALU control input using a small control unit that has as inputs the function field of the instruction and a 2-bit control field, which we call ALUOp.
ALUOp indicates whether the operation to be performed should be
add (00) for loads and stores,
subtract (01) for beq,
or determined by the operation encoded in the funct field (10).
The output of the ALU control unit is a 4-bit signal
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38. 4. A Simple Implementation Scheme
Later in this chapter we will see how the ALUOp bits are generated from the main control unit.
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39. 4. A Simple Implementation Scheme
Later in this chapter we will see how the ALUOp bits are generated from the main control unit.
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40. 4. A Simple Implementation Scheme
This truth table shows how the 4-bit ALU control is set depending on these two input fields.
don’t-care term: An element of a logical function in which the output does not depend on the values of all the inputs.
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41. 4. A Simple Implementation Scheme
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42. 4. A Simple Implementation Scheme
The op field, which as we saw in Chapter 2 is called the opcode, is always contained in bits 31:26. We will refer to this field as Op[5:0].
The two registers to be read are always specified by the rs and rt fields, at positions 25:21 and 20:16. This is true for the R-type instructions, branch equal, and store.
The base register for load and store instructions is always in bit positions 25:21 (rs).
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43. 4. A Simple Implementation Scheme
The 16-bit off set for branch equal, load, and store is always in positions 15:0.
The destination register is in one of two places.
For a load it is in bit positions 20:16 (rt),
for an R-type instruction it is in bit positions 15:11 (rd).
Thus, we will need to add a multiplexor to select which field of the instruction is used to indicate the register number to be written.
The first design principle from Chapter 2—simplicity favors regularity—pays off here in specifying control.
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44. 4. A Simple Implementation Scheme
We can add the instruction labels and extra multiplexor to the simple datapath.
The write signals for state elements,
The read signal for the data memory, and the control signals for the multiplexors.
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45. 4. A Simple Implementation Scheme
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46. 4. A Simple Implementation Scheme
These nine control signals (seven from Figure 4.16 and two for ALUOp) can now be set on the basis of six input signals to the control unit, which are the opcode bits 31 to 26.
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47. 4. A Simple Implementation Scheme
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48. 4. A Simple Implementation Scheme
Table shows how the control signals should be set for each opcode.
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49. 4. A Simple Implementation Scheme
Let’s design the control unit logic.
How each instruction uses datapath?
The operation of the datapath for an R-type instruction. (add $t1,$t2,$t3)
The operation of the datapath for an store/load instruction. (lw $t1, offset($t2))
The operation of the datapath for a branch instruction.
(beq $t1, $t2, offset)
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50. 4. A Simple Implementation Scheme
(R-type): Although everything occurs in one clock cycle, we can think of four steps to execute the instruction:
The instruction is fetched, and the PC is incremented.
Two registers, $t2 and $t3, are read from the register file; also, the main control unit computes the setting of the control lines during this step.
The ALU operates on the data read from the register file, using the function code (bits 5:0, which is the funct field, of the instruction) to generate the ALU function.
The result from the ALU is written into the register file using bits 15:11 of the instruction to select the destination register ($t1).
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51. 4. A Simple Implementation Scheme
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52. 4. A Simple Implementation Scheme
(store/load): We can think of a load instruction as operating in five steps:
An instruction is fetched from the instruction memory, and the PC is incremented.
A register ($t2) value is read from the register file.
The ALU computes the sum of the value read from the register file and the sign-extended, lower 16 bits of the instruction (offset).
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53. 4. A Simple Implementation Scheme
(store/load): We can think of a load instruction as operating in five steps: (continue)
The sum from the ALU is used as the address for the data memory.
The data from the memory unit is written into the register file; the register destination is given by bits 20:16 of the instruction ($t1).
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54. 4. A Simple Implementation Scheme
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55. 4. A Simple Implementation Scheme
(branch): It operates much like an R-format instruction, but the ALU output is used to determine whether the PC is written with PC + 4 or the branch target address.
An instruction is fetched from the instruction memory, and the PC is incremented.
Two registers, $t1 and $t2, are read from the register file.
The ALU performs a subtract on the data values read from the register file. The value of PC + 4 is added to the sign-extended, lower 16 bits of the instruction (offset) shifted left by two; the result is the branch target address.
The Zero result from the ALU is used to decide which adder result to store into the PC.
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56. 4. A Simple Implementation Scheme
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57. 4. A Simple Implementation Scheme
Let’s continue with the control implementation.
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58. 4. A Simple Implementation Scheme
single-cycle (single clock cycle) implementation: An implementation in which an instruction is executed in one clock cycle.
How the basic datapath and control can be extended to handle other instructions in the instruction set?
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59. 4. A Simple Implementation Scheme
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60. 4. A Simple Implementation Scheme
Although the single-cycle design will work correctly, it would not be used in modern designs because it is inefficient.
The clock cycle must have the same length for every instruction in this single-cycle design. So, the longest possible path in the processor determines the clock cycle.
This path is almost certainly a load instruction, which uses five functional units in series:
*The instruction memory  The register file  The ALU  The data memory  The register file.
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61. 4. A Simple Implementation Scheme
Although the CPI is 1 (see Chapter 1), the overall performance of a single-cycle implementation is likely to be poor, since the clock cycle is too long.
The penalty for using the single-cycle design with a fixed clock cycle is significant, but might be considered acceptable for this small instruction set.
Historically, early computers with very simple instruction sets did use this implementation technique.
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62. 4. A Simple Implementation Scheme
Because we must assume that the clock cycle is equal to the worst-case delay for all instructions, it’s useless to try implementation techniques that reduce the delay of the common case but do not improve the worst-case cycle time.
A singlecycle implementation thus violates the great idea from Chapter 1 of making the common case fast.
So, the solution is Pipelining.
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63. 5. An Overview of Pipelining
Pipelining: An implementation technique in which multiple instructions are overlapped in execution, much like an assembly line.
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64. 5. An Overview of Pipelining
Anyone who has done a lot of laundry has intuitively used pipelining.
The non-pipelined approach to laundry would be as follows:
Place one dirty load of clothes in the washer.
When the washer is finished, place the wet load in the dryer.
When the dryer is finished, place the dry load on a table and fold.
When folding is finished, ask your roommate to put the clothes away.
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65. 5. An Overview of Pipelining
When your roommate is done, start over with the next dirty load.
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66. 5. An Overview of Pipelining
The pipelined approach takes much less time.
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67. 5. An Overview of Pipelining
There are four stages: washing, drying, folding and putting away.
Therefore, pipelined laundry is potentially four times faster than non-pipelined.
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68. 5. An Overview of Pipelining
The same principles apply to processors where we pipeline instruction-execution. MIPS instructions classically take five steps:
Fetch instruction from memory.
Read registers while decoding the instruction. The regular format of MIPS instructions allows reading and decoding to occur simultaneously.
Execute the operation or calculate an address.
Access an operand in data memory.
Write the result into a register.
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69. 5. An Overview of Pipelining
Under ideal conditions and with a large number of instructions, the speed-up from pipelining is approximately equal to the number of pipe stages;
a five-stage pipeline is nearly five times faster.
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70. 5. An Overview of Pipelining
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71. 5. An Overview of Pipelining
IF: Instruction Fetch.
ID: Instruction Decode/register file read stage.
EX: Execution stage.
MEM: Memory access stage.
WB: Write-back stage.
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72. 5. An Overview of Pipelining
Hazards: Situations in pipelining when the next instruction cannot execute in the following clock cycle.
structural hazard: When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute.
data hazards: occur when the pipeline must be stalled because one step must wait for another to complete.
control hazard: arising from the need to make a decision based on the results of one instruction while others are executing.
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73. 6. Pipelined Datapath and Control
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74. 6. Pipelined Datapath and Control
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75. 7. Fallacies and Pitfalls
Fallacy: Pipelining is easy.
Fallacy: Pipelining ideas can be implemented independent of technology.
Pitfall: Failure to consider instruction set design can adversely impact pipelining.
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76. 8. Concluding Remarks
We saw how the datapath for a MIPS processor could be constructed based on the architecture and the decision to build a single-cycle implementation.
Of course, the underlying technology also affects many design decisions by dictating what components can be used in the datapath, as well as whether a single-cycle implementation even makes sense.
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77. 8. Concluding Remarks
Pipelining improves throughput but not the inherent execution time, or instruction latency, of instructions.
Pipelining was presented as reducing the clock cycle time of the simple single-cycle datapath.
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78. Thanks for your
listening