1. Integrated Management of Power Aware Computation and Communication Technologies
Nader Bagherzadeh, Pai H. Chou, Scott Jordan, Fadi Kurdahi University of California, Irvine, ECE Dept.
Jean-Luc Gaudiot University of Southern California, EE-Systems
Nazeeh Aranki, Nikzad “Benny” Toomarian Jet Propulsion Laboratory
Good morning - I am going to present an overview of the IMPACCT project.
This project is jointly proposed by my colleagues and myself at UC Irvine, USC, and JPL.
- In this project, the key word is “integrated”: we are building a hardware/software codesign tool for doing power aware designs.
- Our goal is to give system designers a unified framework for doing design space exploration at the system level.
- The tool should be able to bring together many of the best ideas for power management.
Of course, many great ideas have been developed, and in fact just about everything can have a power management aspect to it.
So, to help us focus our effort, we identified our domain of application, and that is what I will present first.

2. What is IMPAC2T? Hardware/software codesign tool System integration
for power aware designs
bring together many of the best ideas for power management
design space exploration at the system level
System integration
component-based
interface synthesis
power manager synthesis
Power-aware components
parameterizable components library
wrapper around commercial off-the-shelf components

3. Project Participants UC Irvine - Design tools
Nader Bagherzadeh
Pai Chou
Scott Jordan
Fadi Kurdahi
USC - Architectural power optimization
Jean-Luc Gaudiot
JPL - Applications and benchmarking
Nazeeh Aranki
Nikzad “Benny” Toomarian
Team of experts

4. Quad Chart Innovations Impact Component-based power-aware design
Behavior
Innovations
high-level
components
behavioral
system model
high-level
simulation
functional
partitioning
& scheduling
composition
operators
Component-based power-aware design
Multi-power component aggregation
Power-aware reconfigurable architectures
Protocol-based power management
Global power policy optimization
Static & dynamic configurability for power
Architecture
mapping
system integration & synthesis
parameterizable
components
system
architecture
static
configuration
busses, protocols
dynamic power management
Impact
System Modeling
Coordination Synthesis
Architecture Definition
Static Partitioning
Component partitioning
Authoring Tool v1.0
Dynamic Partitioning
Simulator v1.0
Component Partitioning
Fully exploit off-the-shelf components
Unified functional/power correctness
Confidence in complex design points
Rapid turnaround time to architecture
Power protocol for massive scale
Start
End
2Q 00
2Q 01
2Q 02
Kickoff
Power Management Design Techniques
PCL definition
Simulatable components
Benchmark Identification
Component Simulator
PCL benchmarking
Synthesizable components
System Benchmarking

5. Power aware technologies are essential for future deep space missions
Applications
Past Missions
Future Missions
Power aware technologies are essential for future deep space missions
Our driving application will be these miniaturie vehicles. These aresmall autonomous or reomote-controlled vehicles with wheels or wings. It’s great to send one or more of these vehicles to places where it might be hazardous or impossible for humans to go.

6. Challenges for the X2000 Design goals Systems engineering methodology
Low power and high performance designs
Low activation rates and power management
X2000 target is 10-20x reduction in power
Design for technology scaling.
Design for long-term survivability
Systems engineering methodology
Design, simulation, verification and synthesis.
Use design automation / integration tools.
Power management was 50% of the weight; power management overhead
Multi-mission requirement - ability to configure for different missions
Fault tolerance

7. PA System Architecture
The NASA X2000 Avionics System
high-rate input
symmetric
multiprocessor
modules
reconfigurable
hardware blocks
communication
module (CDMA)
(camera)
high-speed bus
(e.g. IEEE 1394)
low-speed bus
(e.g. I2C )
bus power
controller
microcontroller-directed subnet
- power regulations & control
- analog telemetry sensors
- safety inhibits
- valve & pyro drive
altimeter
subnet

8. Previous Work Design Tools Components Architectural platform
System-Level: the Chinook HW/SW codesign tool
Architectural synthesis (w/ physical design considerations)
Components
Reconfigurable computing: the MorphoSys Chip
Parameterizable components: PCL
Simultaneous MultiThreading vs. Chip MultiProcessing
Architectural platform
Segmented bus X-2000, Mars Pathfinder
Configurable SMP
Design tools
At UCI we have experiences in system leve design tools and architectural synthesis.
Components (list them)
both at UCI and USC.
- MorphoSys project, which is another DARPA funded reconfigurable computing project.
- it is one of the components we will be using to gain experience
- parameterizable component library
- SMT

9. Background: MorphoSys Project
Advanced RISC
Processor
MorphoSys
Reconfigurable
Processor Array
Reconfigurable processor array
MIPS-like RISC processor
High-bandwidth data interface
100 MHz clock
0.35µm 4metal CMOS
Software support
Platform for dynamic power management
System Bus
Instr./Data
Cache (L1)
High Bandwidth
Data Interface
External Memory
(e.g. SDRAM, RDRAM)
what are these components?
- hardware or software processes
- high-level logical components vs. concrete components.

10. Background: Chinook project
Component-based HW/SW codesign framework
Specification, simulation, synthesis
Motivated by IP reuse, system integration
Problem: IP Reuse forces modification
Reason: components have hardwired coordination protocols
Approach
Adaptable components
Separate coordination protocols from components
Benefits
Reuse without modification
Enable system-level optimizations
Previously, I worked on a hardware/software codesign tool. called Chinook at the Uiv of Washington. It was jointly funded by DARPA and NSF.
The distinguishing features of Chinook are that it is component based. It helps designer with system integration by interfacing the components. We don’t go inside the components. IP-based design is one of the gaols of JPL - wanted to use only COTS, because it not only helps them cut down on the cost, but more importantly help them meet their schedule.
But one of the fundamental obstacles by IP-based design is components can’t be integrated w/out modification. This is not just simple modifications to the interfaces; but these require you to go inside and make intricate modifications.
And we believe we’ve made some breakthrough in this area. We came up with a new way of packaging the components and a new way of composing them.
We made the observation that in order to compose components, they need to”speak the same protocol; otherwise, modificaiton is necessary.
I am a cofounder of a startup company that is commercializing this work.

11. Example protocol: Subsumption
joystick
bumper
sonar
wheels
escape
avoid
override s
sensors
actuators
decision
modules
composition
Must handle three cases:
Subsuming, yielding, idle
Hardwired protocol
Generalization:
Adaptable components (by mode mapping)
Separate protocols & components y s i s i i y y i s i
+subsuming
as an example of a COORDINATION protocol, consider the case of a mobile robot, which is a simpler way to illustrate similar concpets as foundi n the X-2000.
- system can be organized as a set of coordinated concurrent processes.
- subsumption architecture [Rodney Brooks]
for the purpose of composition, each process must behave like a 3-state FSM: - idle, yield, and subsuming.
As long as everybody behaves according to this protocol, they can be composed.
- of course the controller for coordinating these processes must be synthesized, but there is a lot of freedom --- in fact they can be optimized for centralized or distributed.
- claim earlier about being able to compose w/out modification: how?
- package up a process by exposing modes as an interface, not just data ports.
- example: module for controlling robot: forward, back, wait, turn.
- does not speak subsumption -> but can be adapted to the requiredi nterface
by mapping. so F maps to idle,
detect event back/wait/turn -> subsuming,
- once this is adapted, it can be composed just like any other subsumption component w/out concerns about whether it’s a bumper or arm underneath. y s y
subsumption
interface
idle B F
subsuming
idle
subsuming
yielding
subsuming W
yielding s s i i
Bumper
process
release y y i F B W B W T W 2s F B T s i
45d
bump +B +W

12. Power-aware coordination
Protocols
Coordinate power usage
e.g. peak power, resource arbitration
Multiple versions of given algorithm
Components
Adaptable to different power management policies, not hardwired
Usable in new applications even if not designed to be power aware!
Synthesis
Coordination controller (“mode manager”)
Depends on architectural mapping.

13. Architectural mapping
Single processor or multiple processors
Multiple mappings to an architecture
mode
manager
modal
processes

14. Distributed mode managers
Automatically partitioned among processors
synthesized control communication
comm. tradeoffs: synchronization, replication
mode
manager
modal
processes

15. IMPAC2T overview Behavior Architecture mapping
high-level
components
behavioral
system model
high-level
simulation
composition
operators
functional
partitioning
& scheduling
Architecture
mapping
impact is a hardware software codesign tool
- behavioral (architecture independent) vs. system architectural. level.
system integration & synthesis
parameterizable
components
system
architecture
static
configuration
busses, protocols
dynamic power management

16. Innovations Specification Architecture
Component-based power-aware design
Protocol-based power management
Multi-power component aggregation
Architecture
Power-aware reconfigurable architectures
Static & dynamic configurability for power
Global power policy optimization
Synthesized power manager (centralized and distributed)

17. Impact Productivity Massive Scalability Robust methodology
Fully exploit off-the-shelf components
Rapid turnaround time to architecture
Massive Scalability
Protocol based power management
System architecture platform
Robust methodology
Unified functional/power correctness
Confidence in complex design points

18. Technology Transition
JPL
first users of this tool
Commercialization
startup company
The technology transfer plan is to have JPL use this tool for the development of theX2000.

19. Milestones 2Q 00 2Q 01 2Q 02 Kickoff System Modeling
Coordination Synthesis
Architecture Definition
Static Partitioning
Component partitioning
Authoring Tool v1.0
Dynamic Partitioning
Simulator v1.0
Component Partitioning
2Q 00
2Q 01
2Q 02
Kickoff
Power management design techniques
PCL definition
Simulatable components
Benchmark Identification
Component Simulator
PCL benchmarking
Synthesizable components
System Benchmarking

20. Conclusion Co-design framework
Component-based parameterization and integration
Commercial off-the-shelf and DARPA-community designs (ND’s Morphable architecture)
Supports high-level coordination, dynamic management of power/performance
Design space exploration tool for DARPA community
JPL, DADS

21. Partitioning & Integration
Static partitioning
Map behavioral description onto the elements in the architecture
Component => processor
Channel => bus
Dynamic partitioning
Multi-version components
Applicable to hardware, software, and mixed
Complements middleware / object migration
System integration mechanisms
Synthesized/optimized power-timing coordination controller
Mode managers + coordination protocols
High-level knowledge enables tradeoffs and optimization

22. Simulation and Analysis
System level validation and analysis
Components
Coordination protocols
Systems
Support the exploration of design space
Metrics: cost, area, performance, power
Must capture low level and data type effect
Interaction with simulators
Back annotation interface to (commercial) low-level simulators

23. Parameterizable Component Library
Levels of abstraction
Analyzable
Simulatable
Synthesizable
Synthesized
Component characterization
Register level decomposition
Analysis of power consumption
VLSI layout size
Performance by simulation

24. Power-Aware Design Methodology
Support Provided
Design Stage
Component Evaluation
Behavioral Composition
Architectural Exploration
Premission Configuration
Dynamic power management
Parameterized component library Accurate hw/sw power estimation Power-aware microarchitecture
Higher-order operators for power coordination Multi-implementation components Synthesis/optimization of coordination controllers
System-level simulation and analysis Power-aware hw/sw partitioning
Scalable, reconfigurable multiprocessor arch. Synthesized power manager for mission planning
Arch. support for hw/sw process migration Pre-mission power/real-time scheduling

25. Outline Research Organization Quad Chart
Previous Relevant Efforts by PI’s
Proposed Work
Innovations
Application Domain
Technology Transfer

26. Low level components have detailed power estimates
Tool Flow
Each high level component encapsulates one or more low level components
Low level components have detailed power estimates