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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
8051 Instruction Set 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Introduction The 8051 instruction set is optimized for 8-bit control applications. It provides a variety of fast, compact addressing modes for accessing the internal RAM to facilitate operations on small data structures. 8051 instructions have 8-bit op-codes. The 8051 has 255 instructions. There are byte instructions, 92 2-byte instructions, and 24 3-byte instructions 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
8051 Addressing Modes Five addressing modes are available: Immediate Register Direct Indirect Indexed There are three more modes: Relative Absolute Long These are used with calls, branches and jumps and are handled automatically by the assembler. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Structure of Assembly Language
[ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Immediate Addressing The data is directly specified in the instruction. Useful for getting constants into registers. Immediate data must be preceded with a “#” sign. MOV R0, #85H ; Load R0 with the value 85H MOV R0, #0F0H ; Load R0 with the value F0H The immediate value is a maximum of 8-bits. One exception, when dealing with the DPTR register it can be 16-bits. MOV DPTR, #2000H ; Load the value 2000H into the DPTR register 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Register Addressing The register addressing instruction involves information transfer between registers Direct access to eight registers – R0 through R7. MOV A, R0 MOV R1, A Not all combinations are valid. MOV R2, R1 ; Invalid There are 4 banks of registers accessible through register addressing. Only one bank can be accessed at a time controllable through bit RS0 and RS1 of the PSW. MOV PSW, # B Set RS0:RS1 to 11, therefore, accessing register bank 3. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Direct Addressing Direct addressing can access any on-chip hardware register by their address OR access any memory location by its address. All on-chip memory locations and registers have 8-bit addresses. Can use the 8-bit address in the instruction. MOV A, 4H ; Amem[04H] Don’t get confused with Immediate mode. No “#” sign. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Indirect Addressing R0 and R1 may be used as pointer registers where their contents indicate an address in internal RAM where the data is to be read or written. Indirect addressing is represented by a commercial "at" sign preceding R0 or R1 MOV R1, #40H ; Make R1 point to location 40 MOV ; Move the contents of 40H to A R1 ; Move contents of R1 into the ; memory location pointed to by R0. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Indirect Addressing(Contd)
Can also be used for accessing external memory: Can use R0 and R1 to point to external memory locations 00H to FFH. MOVX ; Move contents of external memory location whose address is in R1 into A Can also use DPTR to point to all 64k of external memory. MOVX Indirect addressing is essential when stepping through sequential memory locations. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Indexed Addressing The Indexed addressing is useful when there is a need to retrieve data from a look-up table A 16-bit register (data pointer) holds the base address and the accumulator holds an 8-bit displacement or index value Use a register for storing a pointer to memory and another register for storing an offset. The effective address is the sum of the two: EA = Pointer + Offset MOVC ; Move byte from memory located at DPTR+A to A. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Relative Addressing Used only with certain jump instructions Relative address (or offset) is an 8-bit signed value, which is added to the program counter to form the address of the next instruction executed The range for jumping is -128 to +127 locations Relative offset is appended to the instruction as an additional byte Prior to the addition, the program counter is incremented to the address following the jump instruction; thus. the new address is relative to the next instruction, not the address of the jump instruction. Advantage - providing position-independent code Disadvantage - jump destinations are limited in range 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Absolute Addressing Two instructions associated with this mode of addressing are ACALL and AJMP instructions These are 2-byte instructions where the 11-bit absolute address is specified as the operand These 2-byte instructions allow branching within the current 2K page of code memory. The upper 5 bits of the 16-bit PC address are not modified. The lower 11 bits are loaded from this instruction. So, the branch address must be within the current 2K byte page of program memory (211 = 2048) Advantage - short (2-byte) instructions Disadvantages - limiting the range for the destination and providing position dependent code 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Long Addressing This mode of addressing is used with the LCALL and LJMP instructions. These 3-byte instructions include a full 16-bit destination address as bytes 2 and 3 of the instruction. It allows use of the full 64K code space Advantage - full 64K code space may be used Disadvantage - the instructions are three bytes long and are position-dependent 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
INSTRUCTION TYPES The instructions are grouped into 5 groups Arithmetic Logic Data Transfer Boolean Branching 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Introduction to Keil uvision-3 IDE tool Demo
Introduce keil software to students so that they can use those instructions and do practically in keil IDE.. All those instructions on slide can be done in keil. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Arithmetic Instructions
Arithmetic instructions perform several basic arithmetic operations such as addition, subtraction, division, multiplication etc. After execution, the result is stored in the Accumulator. The appropriate status bits in the PSW are set when specific conditions are met. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Arithmetic Instructions
Since four addressing modes are possible, the ADD instruction can be written in different ways: ADD A, 7FH (direct addressing) ADD (indirect addressing) ADD A, R7 (register addressing) ADD A, #35H (immediate addressing) 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Arithmetic Instructions
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Logical Operations Logical instructions perform Boolean operations (AND, OR, XOR, and NOT) on data bytes on a bit b y bit basis Work on byte sized operands or the CY flag. ANL A, Rn ANL A, direct ANL ANL A, #data ANL direct, A ANL direct, #data ANL C, bit ANL C, /bit 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Logical Operations 11/11/2018
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Data Transfer Instructions
Data transfer instructions can be used to transfer data between an internal RAM location and an SFR location without going through the accumulator It is also possible to transfer data between the internal and external RAM by using indirect addressing 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Data Transfer Instructions
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Boolean Operation Instructions
can perform single bit operations This group allows manipulating the individual bits of bit addressable registers and memory locations as well as the CY f lag. The P, OV, and AC flags cannot be directly altered. This group includes: Set, clear, and, or complement, move. Conditional jumps. 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Boolean Operation Instructions
Mnemonic Description CLR C Clear C CLR bit Clear direct bit SETB C Set C SETB bit Set direct bit CPL C Complement c CPL bit Complement direct bit ANL C,bit AND bit with C ANL C,/bit AND NOT bit with C ORL C,bit OR bit with C ORL C,/bit OR NOT bit with C MOV C,bit MOV bit to C MOV bit,C MOV C to bit JC rel Jump if C set JNC rel Jump if C not set JB bit,rel Jump if specified bit set JNB bit,rel Jump if specified bit not set JBC bit,rel if specified bit set then clear it and jump
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Program Branching Instructions
Program branching instructions are used to control the flow of program execution Some instructions provide decision making capabilities before transferring control to other parts of the program (conditional branches). Three variations of the JMP instruction: SJMP, LJMP, and AJMP (using relative, long, and absolute addressing, respectively) 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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Program Branching Instructions
Mnemonic Description ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump JMP @A+DPTR Jump indirect JZ rel Jump if A=0 JNZ rel Jump if A NOT=0 CJNE A, direct,rel Compare and Jump if Not Equal CJNE A, #data,rel CJNE Rn, #data,rel CJNE @Ri, #data,rel DJNZ Rn,rel Decrement and Jump if Not Zero DJNZ direct,rel NOP No Operation 11/11/2018
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SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
Thank you 11/11/2018 SCHOOL OF ELECTRONICS ENGINEERING Electronics and Communication
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