Introduction to Micro Controllers & Embedded System Design Microprocessor/Microcontroller Department of Electrical & Computer Engineering Missouri University.

Introduction to Micro Controllers & Embedded System Design Microprocessor/Microcontroller
Department of Electrical & Computer Engineering Missouri University of Science & Technology A.R. Hurson

Introduction to Micro Controllers & Embedded System Design
Note, this unit will be covered in three lectures. In case you pre-test it, then you have the following options: 1) Take the early test and start module4 2) Study the supplement module (supplement.module3) 3) Act as a helper to help other students in studying module1 Note, options 2 and 3 have extra credits as noted in course outline.

  Introduction to Micro Controllers & Embedded System Design
Enforcement of background Glossary of prerequisite topics No Familiar with the topics? Review background for this module Yes Take Test At the end: take exam, record the score, impose remedial action if not successful No Pass? Remedial action  Yes Glossary of topics Current Module No Familiar with the topics? Take the Module Yes Take Test No Pass? Yes Options Lead a group of students in this module (extra credits)? Study next module? Study more advanced related topics (extra credits)? Extra Curricular activities

Microprocessor: a general purpose computer that is contained in a single integrated circuit (all peripherals are off the CPU chip). In another words, it is a CPU on chip. A system designer using a microprocessor must add memory, I/O devices, … on need basis, externally. Examples include Intel’s x86 family, Motorola’s 860x0 family, … A.R. Hurson

A sample microprocessor
Block diagram of the architecture of the Z80 microprocessor showing: the arithmetic and logic section, register file, control logic section, and buffers to external address and data lines. A.R. Hurson

A sample microprocessor
Z80 Architecture A.R. Hurson Source:

Originally, the concept of microprocessor introduced in early 70s (4-bit Intel 4004)
As the technology advanced and chip density increased, so did the functionality and complexity of a microprocessor. Word size changed from 4-bit to 64-bit, Floating point operations were added, and CPU caches were introduced. A.R. Hurson

Microcontroller: A microprocessor with a number of integrated peripherals, typically used in control- oriented applications (everything is on one chip). Typically, it contains a CPU (could be more than one), memory, and I/O peripherals. Microcontrollers are designed for embedded applications. A.R. Hurson

General architecture of a Microcontroller
A.R. Hurson Source: elprocus.com

General architecture of a Microcontroller
CPU: Central Processing Unit RAM: Random Access Memory ROM: Read Only Memory I/O ports: Parallel I/O port and Serial I/O port ADC: Analog to Digital Converter and Digital to Analog Converter Timers: to be used for various functions such as, lock functions, modulations, pulse generation, … Interrupt A.R. Hurson

Embedded systems: An embedded system is a computer system with a dedicated functionality within a larger mechanical or electrical system, often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. Embedded systems control many devices in common use today. Ninety-eight percent of all microprocessors are manufactured as components of embedded systems. A.R. Hurson Source:

Embedded systems Compared to general-purpose computers, typically embedded computers are low power consumption, small size, rugged operating ranges, and low per-unit cost. These advantages comes at the cost of limited processing capabilities, which make them significantly more difficult to program and to interact with. Embedded systems are commonly found in consumer, cooking, industrial, automotive, medical, commercial, and military applications. A.R. Hurson

Attributes of Embedded devices
Embedded system is something that was not designed to be general purpose, Embedded devices are usually tuned for one or a few applications, Most embedded devices embody the capability they perform, Embedded systems are often commodities rather than capital items themselves, Embedded systems are devices users purchase for a reason that is not thought of as “computing”. A.R. Hurson

Block diagram of a microprocessor/microcontroller system
P U Address bus (16 lines) RAM ROM Interface circuitry Control bus (6 lines) Data bus (8 lines) Peripheral devices A.R. Hurson

Intel 8051 family Company Processor Year Intel 4004 4-bit 1971
1974 Intel 8048 1976 Intel 8031 8-bit (ROM less) Intel 8051 8-bit (Mask ROM) 1980 Intel 8086 16-bit 1978 Atmel At89C51 8-bit (Flash Memory) 1984 Microchip PIC16C64 1985 Motorola 68HC11 8-bit (ON chip ADC AVR 8-bit RISC 1996 A.R. Hurson

Features of various Intel microcontroller
8051 8052 8031 8032 8751 8752 4K bytes ROM 8K bytes 0K EPROM 128 bytes RAM 256 bytes 2 Timers 3 Timers A.R. Hurson

Bit-addressable locations
Features of MCS-51 Feature Quantity ROM 4K bytes RAM 128 bytes I/O Ports 4 (8-bit) I/O Pins 32 Serial port 1 Interrupt sources 6 Two 16 bits timers External code memory 64K bytes External data memory Boolean processor Bit slice Bit-addressable locations 210 Multiply/divide 4s A.R. Hurson

Address, data, and control buses
Detailed block diagram of a microprocessor/microcontroller C P U Address, data, and control buses RAM ROM Parallel device Parallel interface Serial interface Interrupt control Timer Serial device External interrupts clocks Internal A.R. Hurson

Central Processing Unit: Monitors and controls all operations performed on the microcontroller. It reads program instructions from ROM memory and executes them. A.R. Hurson

Interrupts It is a subroutine call that interrupts (pauses) the Intel 8051’s main operations or work and causes it to execute any other program, which is more important at the time of operation. Generally five interrupt sources are recognized in Microcontroller. When a subroutine is completed, the execution of main program resumes. A.R. Hurson

Memory Read Only Memory (ROM) or program memory is 4K bytes.
Random Access Memory (RAM) or data memory is 128 bytes. A.R. Hurson

BUS Address Bus is a 16-bit bus to address memory location
Data Bus is an 8-bit bus to transfer data A.R. Hurson

Input/Output Port: Intel 8051 has four 8-bit parallel and one serial I/O ports.
A.R. Hurson

Pin Configuration AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P0.7 P0.6 P0.5 P0.4
32 33 34 35 36 37 38 39 8 7 6 5 4 3 2 1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 28 27 26 25 24 23 22 21 17 16 15 14 13 12 11 10 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 RD WR T1 T0 INT1 INT0 TXD RXD 29 30 31 9 40 VCC VSS 19 18 20 RST XTL2 PSEN ALE EA XTL1 A15 A14 A13 A12 A11 A10 A9 A8 Pin Configuration A.R. Hurson

Port0 (Pins 32 to 39) is a dual-purpose port
Port0 (Pins 32 to 39) is a dual-purpose port. In minimum configuration design, it is a general purpose I/O port. For larger designs with external memory, it becomes a multiplexed address and data bus. Port1 (Pins 1 to 8) is a dedicated I/O port and available to external devices as required. In 8032/8052 configurations, P1.0 and P1.1 are used either as I/O lines or as an external inputs to the third timer. Port2 (Pins 21 to 28) is also a dual-purpose port serving as general purpose I/O or as the high byte of the address bus for designs with external memory of 64K bytes. A.R. Hurson

Port3 (Pin 10 to 17) is another dual purpose port
Port3 (Pin 10 to 17) is another dual purpose port. It is either a general purpose I/O or they are multifunctional, each having alternate purpose as follows: Bit Name Bit address Alternate function P3.0 RXD B0H Receive data for serial port P3.1 TXD B1H Transmit data for serial port P3.2 B2H External interrupt P3.3 B3H P3.4 T0 B4H Timer/counter external input P3.5 T1 B5H P3.6 B6H External data memory write strobe P3.7 B7H External data memory read strobe P1.0 T2 90H P1.1 T2EX 91H Timer/counter capture/reload A.R. Hurson

Program Store Enable (Pin 29) is a controll signal that enables external program memory (note: 8051 has four dedicated control signals). It is usually connected to an EPROM output enable pin. PSEN signal pulses low during the fetch cycle of an instruction stored in external program memory. The op.code is read from memory, travels across data bus, and latches into instruction register for decoding. When executing program from internal ROM memory PSEN remains in inactive (high) state. A.R. Hurson

Address Latch Enable (Pin 30) is used de-multiplexing the address and data bus when port 0 is used in its alternate modes (i.e., as the data bus and the low-byte of the address bus). ALE is the signal that latches the address into an external register during the 1st half of a memory cycle. Then the port 0 lines are available for data input or output during the 2nd half of the memory cycle when data transfer takes place. A.R. Hurson

External Access (Pin 31) is generally tied high (+5 volts) or low (ground). If high the 8051/8052 executes programs from internal ROM memory. If low, programs execute from external memory only. On-chip Oscillator inputs (Pins 18 & 19) − These pins are used for interfacing an external crystal to get the system clock. A.R. Hurson

Reset (Pin 9) is the master RESET for 8051
Reset (Pin 9) is the master RESET for When this signal is high for at least two machine cycles, the internal registers are loaded with initial values in an orderly system start-up. For normal operation, RST is low. Power connection (Pines 20 & 40) 8051 operate from a signal +5 volts supply. The Vcc connection is on pin 40 and Vss connection (ground) is on pin 20. A.R. Hurson

Address, data, and control buses
Detailed block diagram of a microprocessor/microcontroller C P U Address, data, and control buses RAM ROM Parallel device Parallel interface Serial interface Interrupt control Timer Serial device External interrupts clocks Internal A.R. Hurson

Memory organization Most microprocessors like other computers use a random access memory for both programs and data (i.e., stored program machine). This is not the case for microcontroller systems (say why?). In case of 8051/8052 internal memory consists of on-chip ROM (program memory) and on-chip RAM (data memory). The on-chip RAM contains a rich arrangement of general- purpose storage, bit addressable storage, register banks, and special function registers. A.R. Hurson

Memory organization Note: Registers and Input/Output ports are memory mapped and accessible like any other memory location. Stack resides within the internal RAM. A.R. Hurson

Memory organization In general, RAM memory can be partitioned into three groups: 32 bytes from locations 00H to 1FH are register banks and stack. These 32 bytes are divided into four banks of registers. 16 bytes from locations 20H to 2FH are bit addressable memory. 80 bytes from locations 30H to 7FH are scratch pad memory. This section is used for the purpose of storing data and parameters by the programmers. A.R. Hurson

Memory organization General purpose RAM Bit addressable locations
7F 30 2F 20 1F 18 17 10 0F 08 07 00 General purpose RAM Bank3 Bank2 Bank1 Bank0 Bit addressable locations Byte address A.R. Hurson

Byte address Byte address 90 8D 8C 8B 8A 89 88 87 83 82 81 80 P1 TH1
TL1 TL0 TMOD TCON PCON DPH DPL SP P0 FF F0 E0 D0 B8 B0 A8 A0 99 98 Byte address B ACC PSW IP P3 IE P2 SBUF SCON A.R. Hurson

Memory organization Example: State the contents of RAM locations after execution of the following sequence of instructions. MOV R0, #99H ; Load R0 with value 99H MOV R1, #85H ; Load R1 with value 85H MOV R2, #3FH ; Load R2 with value 3FH MOV R7, #63H ; Load R7 with value 63H MOV R5, #12H ; Load R5 with value 12H RAM location 0 has value 99H RAM location 1 has value 85H RAM location 2 has value 3FH RAM location 7 has value 63H RAM location 5 has value 12H A.R. Hurson

Memory organization Example: State the contents of RAM locations after execution of the following sequence of instructions. SETB PSW, 4 ; Select bank2 MOV R0, #99H ; Load R0 with value 99H MOV R1, #85H ; Load R1 with value 85H MOV R2, #3FH ; Load R2 with value 3FH MOV R7, #63H ; Load R7 with value 63H MOV R5, #12H ; Load R5 with value 12H RAM location 10 has value 99H RAM location 11 has value 85H RAM location 12 has value 3FH RAM location 17 has value 63H RAM location 15 has value 12H A.R. Hurson

Bit addressable RAM 8051 has 210 bit addressable locations, of which 128 are at byte addresses 20H through 2FH and the rest are the special function registers. Bit addressability allows one to set, clear, perform AND, OR, … operations at bit level with a single instruction. This is a powerful feature, otherwise, bit processing should have been done as a sequence of read, modify, and write. Finally, I/O ports are bit addressable, as well. A.R. Hurson

Bit addressable RAM For example: SETB 67H
sets bit 67H, which is the most significant bit of “byte address 2CH”. If bit addressability did not exist, one had to write the following code to accomplish the aforementioned task: MOV A, 2CH ORL A, # B MOV 2CH, A A.R. Hurson

Register Banks are located at the lower 32 words of internal RAM memory. The instruction set of supports 8 registers R0 through R7 which are at addresses 00H-07H. A.R. Hurson

Register Banks Example MOV A, R5
is a byte instruction using register addressing mode. Similarly, we can perform the same operation using the following instruction: MOV A, 05H which is a 2 byte instruction (since it is using a direct addressing) A.R. Hurson

Register Banks The active register bank can be altered by changing the register bank select bits in the program status word. Example: Assuming register bank3 is active then, MOV R0, A Writes the content of accumulator into location 18H. A.R. Hurson

Special function registers
Internal registers can be implicitly accessed by instructions. For example INC A increments the accumulator. There are 21 special function registers located at address 80H to FFH. Most of the special function registers are accessed via direct addressing. A.R. Hurson

Program Status Word is at address D0H and contains status bits as follows:
Symbol Address Semantic PSW.7 CY D7H Carry flag PSW.6 AC D6H Auxiliary carry flag PSW.5 F0 D5H Flag0 PSW.4 RS1 D4H Register bank select1 PSW.3 RS0 D3H Register bank select0 bank0 00H-07H bank1 08H-0FH bank2 10H-17H bank3 18H-1FH PSW.2 OV D2H Overflow flag PSW.1 D1H Reserved PSW.0 P D0H Even Parity flag A.R. Hurson

Carry flag has a dual purpose:
It is used to hold the carry out (borrow out) for addition (subtraction) operation. For example, if accumulator has the value FFH then ADD A, #1 sets the accumulator to 00H and sets the carry flag in PSW. It is also used as a “Boolean accumulator” For example, ANL C, 25H ANDs bit 25H with the carry flag and places the result back in carry flag. A.R. Hurson

Auxiliary carry flag is used when performing BCD operations.
Flag0 is a general-purpose flag bit available for user application. A.R. Hurson

Register Bank Select determines the active register bank.
For example: SETB RS1 SETB RS0 MOV A, R7 makes register bank 3 active and moves contents of R7 (at address1FH) to accumulator. A.R. Hurson

Program Status Word is at address D0H and contains status bits as follows:
Symbol Address Semantic PSW.7 CY D7H Carry flag PSW.6 AC D6H Auxiliary carry flag PSW.5 F0 D5H Flag0 PSW.4 RS1 D4H Register bank select1 PSW.3 RS0 D3H Register bank select0 bank0 00H-07H bank1 08H-0FH bank2 10H-17H bank3 18H-1FH PSW.2 OV D2H Overflow flag PSW.1 D1H Reserved PSW.0 P D0H Even Parity flag A.R. Hurson

Overflow flag is set after addition or subtraction operation, if there was an arithmetic overflow (underflow). For example the following operation 0F + 7F = 8E sets the OV bit. A.R. Hurson

Parity bit is automatically set or cleared in each machine cycle to establish even parity of accumulator, i.e., the number of 1s in accumulator plus the P bit is always even. For example if accumulator contains , P will be set to 1. A.R. Hurson

Example Show the status of CY, AC, and P after the following operations: MOV A, #38H ADD A, #2FH + 2F CY = 0 ; Since there is no carry out AC = 1 ; Since there is a carry from D3 to D4 P = 1 ; Since accumulator has five 1s (an odd number of 1s) A.R. Hurson

Example Show the status of CY, AC, and P after the following operations: MOV A, #9CH ADD A, #64H 9C CY = 1 ; Since there is a carry out AC = 1 ; Since there is a carry from D3 to D4 P = 0 ; Since accumulator has 0 1s (an even number of 1s) A.R. Hurson

Example Show the status of CY, AC, and P after the following operations: MOV A, #88H ADD A, #93H 11B CY = 1 ; Since there is a carry out AC = 0 ; Since there is no carry from D3 to D4 P = 0 ; Since accumulator has 4 1s (an even number of 1s) A.R. Hurson

B register is a sort of accumulator at address F0H
B register is a sort of accumulator at address F0H. It is used along with accumulator for multiply and divide operations. The MUL AB multiplies contents of A and B and stores the 16 bit result in A (low-byte) and B (high- byte). The DIV AB divides A by B leaving the quotient in A and remainder in B. B can be also treated as a general-purpose register. It is also bit addressable through bit addresses F0H to F7H. A.R. Hurson

Stack operations are Push and Pop.
Stack pointer is an 8-bit register at address 81H. It contains the address of data item currently on top of stack. The default value (i. e., when the 8051 is powered up) for stack pointer is 07H. This means that RAM location o8 is the first location used by the stack. Stack operations are Push and Pop. Pushing an item to stack increments SP before writing the data and popping from stack reads data and then decrements SP. The stack in 8051 is kept in internal RAM (the first 128 bytes of on- chip RAM) and is limited to addresses accessible by indirect addressing. A.R. Hurson

Example: Initializing the SP with the stack beginning at 60H we have:
MOV SP, #5FH (say why?) Note to push an element into stack, stack pointer is incremented first) This limits the stack to 32 bytes (say why?) A.R. Hurson

Example: Show the snap shots of the stack and stack pointer after execution of the following instructions : MOV R6, #25H MOV R1, #12H MOV R4, #0F3H PUSH 6 PUSH 1 PUSH 4 A.R. Hurson

08 0B 0A 09  SP=08 PUSH 6 25 08 0B 0A 09  SP=09 PUSH 1 25 12 08 0B
MOV R6, #25H MOV R1, #12H MOV R4, #0F3H PUSH 6 PUSH 1 PUSH 4 08 0B 0A 09  SP=08 PUSH 6 25 08 0B 0A 09  SP=09 PUSH 1 25 12 08 0B 0A 09  SP=0A PUSH 4 25 12 F3 08 0B 0A 09  Start SP=07 A.R. Hurson

Example: Show the snap shots of the stack and stack pointer after execution of the following instructions: POP ; Pop stack into R3 POP ; Pop stack into R5 POP ; Pop stack into R2 A.R. Hurson

Initial Configuration
POP ; Pop stack into R3 POP ; Pop stack into R5 POP ; Pop stack into R2 08 0B 0A 09  SP=0B Initial Configuration 6C 76 F9 54 08 0B 0A 09  SP=0A POP 3 6C 76 F9 08 0B 0A 09  SP=09 POP 5 6C 76 08 0B 0A 09  SP=08 POP 2 6C A.R. Hurson

Note: Locations 08 to 1FH can be used for the stack
Note: Locations 08 to 1FH can be used for the stack. If in a program, we need more than 24 bytes of stack, then we need to set the stack pointer to point to any locations of 30 to 7FH. A.R. Hurson

Example: Show the snap shots of the stack and stack pointer after execution of the following instructions : MOV SP, #5FH ; Make RAM location 60H ; the first stack location MOV R2, #25H MOV R1, #12H MOV R4, #0F3H PUSH 6 PUSH 1 PUSH 4 A.R. Hurson

MOV SP, #5FH ; Make RAM location 60H
; the first stack location MOV R2, #25H MOV R1, #12H MOV R4, #0F3H PUSH 2 PUSH 1 PUSH 4 60 63 62 61  SP=60 PUSH 2 25 60 63 62 61  SP=61 PUSH 1 25 12 60 63 62 61  SP=62 PUSH 4 25 12 F3 60 63 62 61  Start SP=5F A.R. Hurson

Data pointer is used to access external code or external data memory
Data pointer is used to access external code or external data memory. It is 16-bit register at addresses 82H (DPL-low byte) and 83H (DPH- high point). For example MOV A, #55H MOV DPTR, #1000H MOVX @DPTR, A Writes 55H into external RAM at location 1000H. A.R. Hurson

Byte address Byte address 90 8D 8C 8B 8A 89 88 87 83 82 81 80 P1 TH1
TL1 TL0 TMOD TCON PCON DPH DPL SP P0 FF F0 E0 D0 B8 B0 A8 A0 99 98 Byte address B ACC PSW IP P3 IE P2 SBUF SCON A.R. Hurson

Note: P1.2 to P1.7 are always available as general purpose I/O lines.
Port registers: In 8051 I/O ports consists of port0 at address 80H, port1 at address 90H, port 2 at address A0H, and port 3 at address B0H. Ports 0, 2, and 3 may not be available for I/O if external memory is used. Note: P1.2 to P1.7 are always available as general purpose I/O lines. A.R. Hurson

All ports are bit addressable which provides a powerful interfacing possibilities (it could be turned on and off using a single instruction). For example, if a motor is connected to port 1 bit 7 SETB P1.7 might turn the motor on and CLR P1.7 might turn it off. A.R. Hurson

The following two instructions are equivalent:
The aforementioned instruction used “dot operator” to address a bit within a bit addressable byte location. The assembler performs the necessary conversion. The following two instructions are equivalent: CLR P1.7 CLR 97H A.R. Hurson

For example: Consider the interface to a device with a status bit called BUSY, which is set when the device is busy and clear when it is ready. If BUSY is connected to say port 1 bit 5, then the following loop could be used to wait for the device to become ready: WAIT: JB P1.5, WAIT A.R. Hurson

Note, only TCON is bit-addressable.
Timer registers: 8051 has two 16-bit Timer/counters for timing intervals or counting events. Timer 0 is at address 8AH (TL0, low-byte) and 8CH (TL0, high- byte), and timer 1 is at address 8BH (TL1, low-byte) and 8DH (TL1, high-byte). Time operation is set by the timer mode register (TMOD) at address 89H and timer control register (TCON) at address 88H. Note, only TCON is bit-addressable. A.R. Hurson

Serial port register: contains an on-chip serial port for communication with serial devices. One register, the serial data buffer (SBUF) at address 99H holds both the transmit and receive data. A.R. Hurson

Both registers are bit-addressable.
Interrupt register: has a 5-source, 2 priority level interrupt structure. Interrupts are disabled after a system reset and then enabled by writing to the interrupt enable register (IE) at address A8H. The priority level is set through the interrupt priority register (IP) at address B8H. Both registers are bit-addressable. A.R. Hurson

Power Control Register at address 87H contains different control bits as follows
Symbol Semantic 7 SMOD Double baud rate bit 6 Undefined 5 4 3 GF1 General-Purpose flag bit1 2 GF0 General-Purpose flag bit0 1 PD Power down, set to active power down mode IDL Idle mode, set to activate idle mode A.R. Hurson

Byte address Byte address Interrupt priority Port3 Interrupt enable
90 8D 8C 8B 8A 89 88 87 83 82 81 80 Byte address P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0 FF F0 E0 D0 B8 B0 A8 A0 99 98 Byte address B ACC PSW IP P3 IE P2 SBUF SCON Port1 Timer reg1 Interrupt priority Timer reg0 Port3 Timer mode Interrupt enable Timer control Power Control Port2 Data pointer Serial Buffer reg A.R. Hurson Stack pointer Port0

External Memory When external memory is used port 0 is unavailable as an I/O port. It becomes a multiplexed address (A0-A7) and data (D0-D7) bus with ALE latching the low-byte of the address at the beginning of each external memory cycle. Port 2 is usually (but not always) employed for the high-byte of the address bus. A.R. Hurson

Accessing External Code Memory
External ROM is enabled by the signal. When an external EPROM is used, both ports 0 and 2 are unavailable as general purpose I/O ports. PSEN A.R. Hurson

EPROM D0-D7 A0-A7 PSEN OE A8-A15 Port 2 Port 0 EA ALE 8051 Latch A.R. Hurson

During first half of memory cycle. The low-byte of the address is provided on port 0 and is latched using ALE. During the second half of the memory cycle, port 0 is used as the data bus and data is read or written depending on the operation. A.R. Hurson

8051 machine cycle is 12 oscillator periods. If the on- chip oscillator is driven by a 12 MHz crystal, a machine cycle is 1 s. During a typical machine cycle ALE pulses twice and 2 bytes are read from program memory (if the current instruction is a 1-byte instruction, the 2nd byte is discarded). A.R. Hurson

Accessing External Data Memory
External data memory is enabled by and the alternate pin functions for P3.7 and P3.6. The only access to external data memory is with the MOVX instruction, using either the 16-bit data pointer (DPTR), R0 or R1 as the address register. RD WR A.R. Hurson

RAM may be interfaced to 8051 the same way as EPROM does, except line connects to RAM’s output enable line and connects to the RAM’s line. The connections to the address and data buses are the same as EPROM. RD OE WR W A.R. Hurson

1K RAM D0-D7 A0-A7 PSEN OE A7 P2.0 Port 0 EA ALE 8051 Latch P2.1 A8 RD WR W CS (no connection) +5 V A.R. Hurson

Port 2 is relieved of its alternate function in minimum component systems (configurations that do not use external code memory and only a small amount of external data memory). 8-bit address can access 256-byte page of RAM. If more than one page of RAM is used, then a few bits from port 2 can be used to select a page. A.R. Hurson

Example Assume port 2 bits 0 and 1 are initialized to select a page, the following two instructions reads the contents of the external RAM at address 0050H into the accumulator: MOV R0, #50H MOV A.R. Hurson

Example Assume port 2 bits 0 and 1 are initialized to select a page, the following instructions reads the last address (03FFH) of the external RAM: SETB P2.0 SETB P2.1 MOV R0, #0FFH MOV A.R. Hurson

Some 8-bit registers A B R0 R1 R5 R6 R7 R4 R3 R2 A.R. Hurson

Some 16-bit registers DPH DPL DPTR PC Program Counter A.R. Hurson

Introduction to Micro Controllers & Embedded System Design Microprocessor/Microcontroller Department of Electrical & Computer Engineering Missouri University.

Similar presentations

Presentation on theme: "Introduction to Micro Controllers & Embedded System Design Microprocessor/Microcontroller Department of Electrical & Computer Engineering Missouri University."— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Introduction to Micro Controllers & Embedded System Design Microprocessor/Microcontroller Department of Electrical & Computer Engineering Missouri University.

Similar presentations

Presentation on theme: "Introduction to Micro Controllers & Embedded System Design Microprocessor/Microcontroller Department of Electrical & Computer Engineering Missouri University."— Presentation transcript:

Similar presentations

About project

Feedback