1. Washington University
CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall
Washington University
Fall 2002
Chris Neely, Chris Zuver
Copyright 2002

2. MP1 Packet classification hardware
103
CAM_MASK_1
103
CAM_VALUE_1
Drop
103 72 71 40 39 8 7
Src IP
Dest IP
Src Port
Dest Port
Proto
103
CAM_VALUE_2
103
CAM_MASK_2
match <= ‘1’ when (input = 0xFFFFFFFFFFFFFFFFFFFFFFFFFF”)
else ‘0’;

3. Protocol Headers Cell Header IP Header UDP IP Header Payload PAD
AAL5 Trailer
AAL5 Pad
CPS-UU & CPI
Frame Len
AAL5
AAL5 Frame Checkum

4. State Transitions for processing Packet

5. Additional Notes on the Protocol Wrappers NOTE: Check SOD
DataEn
SOF
EOF
Data
SOC
SOD
SOP/ A I U D - P F
ATM Header
IP Header
Don't care
Frame Trailer
Padding
Payload Data
UDP Header
CLK
Cell Level
Frame Level
IP Level
Data Enabled during frame trailer
Only use these signals to process UDP/IP packets
This cycle is optional. It does not appear in simulation
UDP payload starts 2 cycles after SOP signal.
UDP payload ends with EOF signal.

6. CAM Update Datagram
ATM Header
Packet Len
Source IP address
( 0xC0A81E0D )
(Reserved)
CAM_1_SRC_IP
CAM_MASK_1
… (if necessary)
ToS HL
Ver
Fragment
IP ID
Src Port
Dest Port ( 0x0320 )
Length
Checksum
# CAMs
AAL5 Pad
CPS-UU & CPI
AAL5 Frame Checksum
Frame Len
CAM_1_DEST_IP
CAM_1_PORTS
CAM_1_ PROTO
(PAD)
CAM_2_SRC_IP
CAM_MASK_2
CAM_2_DEST_IP
CAM_2_PORTS
CAM_2_ PROTO }
CAM_VALUE_1
CAM_VALUE_2
Special UDP/IP Datagram updates values of CAM Entries
Allows software-controlled update of CAM registers
Fields alocated for:
CAM_VALUE_1
CAM_MASK_1
CAM_VALUE_2
CAM_MASK_2

7. State Transitions for updating CAMs

8. FPX Hardware Design Flow
Compile circuit (vcom)
Verify
Functionality (vsim)
Constrain
Placement to FPX RAD
Verify that that resulting packets have correct TTL
Test Module with actual traffic input
Synthesize
Logic to Xilinx gate
technology
(Synplicity)
Upload bitfile
To FPX for testing
Place and Route with constraints
(Xilinx)
Verify Post Place & Route Timing (ModelSim)
Generate bitstream
(Xilinx)

9. Downloading and extracting MP1 files

10. Accessing FPGA Design Tools in Sever 201
Tools -> Class -> …
Opening Cygwin and

11. Compiling the design Compiling the tools Simulating the Design
make compile
Simulating the Design
make sim

12. ModelSim Simulation
Screenshots from ModelSim

13. The Testbench
Sample format of Data Input

14. Synthesizing the Design
Screen shots from Synplicity

15. Backend Tools : Generating the Bitstream

16. Testing the design on the FPX
Screen shots of the upload

17. Verifying the Results
Screenshots ..

18. Creating the waveforms
Creating waveforms…

19. Uploading your solutions
Open the page