1. Chapter 6 -- Introduction to Sequential Devices

2. The Sequential Circuit Model
Figure 6.1

3. State Tables and State Diagrams
Figure 6.2

4. Sequential Circuit Example
Figure 6.3

5. TTL Memory Elements

6. SR Latch Characteristics
Figure 6.11
Q* = S + RQ

7. Latch and Flip-flop Timing
Figure 6.4

8. Set Latch
Figure 6.5

9. Reset Latch
Figure 6.6

10. Set-Reset Latch (SR latch)
Figure 6.7

11. NAND SR Latch
Figure 6.8

12. Set-Reset Latch Timing Diagram
Figure 6.9

13. SR Latch Propagation Delays

14. SN74279 Latch with Two Set Inputs
Figure 6.12

15. Gated SR Latch
Figure 6.13

16. Gated SR Latch Characteristics
Figure 6.14
Q* = SC + RQ + C Q

17. Delay Latch (D latch)
Figure 6.15

18. D Latch Characteristics
Figure 6.16
Q* = DC + CQ

19. D Latch Timing Diagram
Figure 6.17

20. D Latch Timing Constraints
Figure 6.18

21. Pulse-Triggered JK Flip-Flop Characteristics
Figure 6.25
Q* = KQ + JQ

22. Pulse-Triggered JK Flip Realization
Figure 6.26

23. The SN7476 Dual Pulse-Triggered JK Flip-Flop
Figure 6.27

24. SN7474 Dual Positive-Edge-Triggered D Flip-Flop
Figure 6.28

25. SN7474 Excitation Table
Figure 6.29

26. SN7474 Flip-Flop Timing Specifications
Figure 6.30

27. Summary of Latch and Flip-Flop Characteristics