1. These chips are operates at 50MHz clock frequency.
MAX EPLDS
Multiple Array Matrix family of EPLDS was introduced by Altera in 1988.
This family consists of 6 chips with gate capacities ranges from 600 to 1200.
These chips are operates at 50MHz clock frequency.
Its architecture is based on Logic Array Block (LAB).
A LAB consists macrocell, expander product term array Programmable Interconnect Array (PIA) and I/O block.
PIA interconnects all the LABs.

2. MAX LAB

3. MAX Macrocell

4. A macrocell consists an array of product terms, and a flip flop.
MAX EPLDS
A macrocell consists an array of product terms, and a flip flop.
The flip flop can be programmed as D, T, JK or SR.
The output of a macrocell is bypassed for combinational functions or passed through latch.
It has a asynchronous preset and clear inputs.
The flip flop is clocked independently or triggered synchronously with other flip flops.
An expander product term array consists a group of uncommitted product terms.

5. An expander product term may feed all the macrocells in LAB.
MAX EPLDS
An expander product term may feed all the macrocells in LAB.
Thus a product term can be shared by other expander product terms.

6. MAX EPLDS
An I/O block consists tri-state buffer and is controlled by a product term of a macrocell.
By disabling the buffer, the macrocell flip flop and I/O pin can be used independently.

7. MAX EPLDS
Altera offers a Programmable Logic Development System software package for implementing designs using MAX EPLDs.
It includes design entry, processing, timing simulation, and device programming.