1. CSC Trigger Update Specific issues:
(Track Finder developments already covered by Padley)
Trigger primitives status
On-chamber electronics (e.g. ALCT) in or nearing production stage
Peripheral crates (e.g. TMB) in final prototype stage
(Simulation issues will be covered by Mumford in next talk)
Specific issues:
Latency
Schedule/manpower
ME1/1 downscope

2. On-Chamber CSC Trigger Electronics
Comparator ASICs now in full production (8000 delivered, left to be tested).
Six ALCT prototypes produced
Successful bench-testing.
Successful radiation test (reload in 45 ms vs 150 ms).
Successful cosmic-ray testing.
Pre-production order for 30 modified ALCT boards placed.
Will seek production approval Dec 3 at ESR.
Good price ($240 for Skewclear® cables negotiated.

3. Power, computer connectors
New ALCT Boards
Power, computer connectors
80 MHz SCSI outputs
(to Trigger Motherboard)
Xilinx ® mezzanine card
Main board
384 ch
Delay/ buffer ASICs,
2:1 bus multiplexers (other side)
Input signal connectors
Analog section:
test pulse generator, AFEB power,
ADCs, DACs (other side)

4. Some Test Results Thresholds: Virtex® loading time (38ms).
(ADC-DAC) +2*Channel vs. DAC setting.
Essentially perfect behavior
Virtex® loading time (38ms).
Virtex power about 1 watt.

5. Delay ASICs

6. Radiation Test of Virtex XCV1000E FPGA
Loop over 64 WG, inject patterns into Delay chips, read out FIFO of Virtex FPGA.
Irradiate Virtex FPGA with
50 pA beam current
100 pA beam current
10 pA beam current
<tSEU>=60.6 Rad compared to 59.2 Rad for previous Altera®…
Improvements:
5 chips -> 1 chip
Loading time 150ms->38ms

7. Virtex FPGA Calculations : 0.16% SEU-affected boards in ME1/1
SEU s*L = 2.7*10-5/s rate per board
SEU s = 2.1*10-9 cm2
L = 1.3*104/cm2/s flux estimate ME1/1
E.g. refresh every 60 s (1 min.)
0.07 % dead time (0.04s/60s)
0.16% SEU-affected boards in ME1/1
<0.04 % in other stations
Slow Control FPGA (Spartan®) 6x more rad-tolerant than Virtex – fewer cells

8. ALCT Modifications Mechanical: Electrical:
Add bolts to hold mezzanine card to ALCT base card.
Move jumpers and some test points out from underneath mezz card.
Electrical:
Rad-tolerant regulator.
Fix power-on latch-up problem.
More precise threshold and power voltage readings (ADC).
Change small capacitors on mezzanine card for better high-frequency filtering.
Add some test points, add clear labels, change power LEDs from green to red (so 1.8v LED will light up)
Etc.

9. ALCT-672 and –288 Versions Preliminary layout by M. Kan (PNPI)
Updates will follow lead of ALCT-384
First boards (7) of ALCT-672 will be ordered late-November

10. ALCT Production Testing
Single-cable testing underway
Find ~6 errors (e.g. solder bridges) per prototype board
External board:
All I/O
FIFOs for dynamic test
Delay chips for 0.25ns adjustment
Boards being assembled (arrive Nov. 15)
Firmware under development

11. CSC Peripheral Crate Electronics
Required for chamber control and readout:
Custom backplane
Done
CCB (Clock & Control board)
5 boards delivered, 10 more being prepared at Rice, firm/software done.
DMB (DAQ Motherboard)
One board delivered to U. Florida,13 more at Ohio State being prepared, firm/software done.
TMB (Trigger Motherboard)
Two boards delivered to UCLA, 16 at assembler, firm/software under development. Expect completion in December.
Required for assembly/transmission of LCTs for track finding:
MPC (Muon Port Card)

12. Trigger Motherboard Hardware
VME 9U card with interfaces to
ALCT (input)
5xCFEB (input)
DMB (DAQ output)
CCB (clocking)
MPC (trigger output)
RPC link boards (optional, input)
20 boards have been produced.
2 boards have been delivered.
Boards are “alive” and I/O being checked via VME control.
Highest priority is feed-through of ALCT readout information to DMB.
16 will be assembled following approval.
Virtex-2 mezzanine card will be designed.
CFEBs
ALCT
(Future: via transition module)
RPC via transition card

13. CSC TF Latency To DT First prototype dataflow
Pre-production prototype data flow
From Muon Port Cards
From Muon Port Cards
Optical receivers
Optical receivers 1
Front FPGAs 1
Front FPGAs
Sector Receiver st.1
Sector Receiver st.2,3
Sector Receiver st.4
To DT 1
Lookup tables 1
Lookup tables
SR/SP board
Channel link transmitters 4
Bunch crossing analyzer (not implemented)
Channel link receivers 1
Extrapolation units
Latency
Latency 2
Bunch crossing analyzer (not implemented) 1
9 Track Assembler units
Sector Processor FPGA 3
Extrapolation units 1
Final selection unit 3 best out of 9
Pt precalculation for 9 muons 2
9 Track Assembler units (memory) 3
Final selection unit 3 best out of 9 1
Output multiplexor
Pt precalculation for best 3 muons
Sector Processor 3 1
Pt assignment (memory) 2
Pt assignment (memory)
Total: 21 BX
Total: 7 BX
To Muon Sorter
To Muon Sorter

14. CSC Latency Update New design definitely meets latency requirement
Step
1st generation Prototypes
Trigger TDR extrapolation
Present best estimate
Comparator signals at TMB input
15 bx
13 bx
A/CLCTs found and combined
26 bx
15.5 bx
Port Card processing and xmit
6 bx
5 bx
4 bx
Optical link
18 bx
SR and SP receive, process, send
27 bx
16.5 bx
11.5 bx
CSC sorting and transmission to Muon Global Trigger
10.5 bx
10 bx
7.5 bx
Total
102.5 bx
78 bx
69.5 bx
Requirement
~81 bx (DT)

15. Schedule for TriDas Components
Prototype 1 tests now complete
Prototype 2 and production somewhat later than Emu components to optimize technology
MPC, SP, CCC modules, backplane (approx):
01-Apr-02 Prototype 2 designs done
Freeze CSC-DT interface
Determine DDU compatibility with OSU module for Emu
30-Sep-02 Prototype 2 construction done
01-Apr-03 Prototype 2 testing done
30-Sep-03 Final designs done
Aug to Oct-04 Production done
01-Apr-05 Installation done
Backplane: about 3 months faster
CSC Sorter module: only 1, design by 8-Jan-04

16. Manpower U. Florida Rice UCLA Physicists: Acosta, Scurlock (student)
Engineers: Madorsky, Golovtsov (PNPI), Uvarov (PNPI)
Rice
Physicists: Padley
Engineers: Matveev, Nussbaum
UCLA
Physicists: Cousins, Hauser, Valouev, Mumford (student)
Engineers: JK

17. ME1/1 Downscope? Presently 2 muons/20o MPC as shown
If ME1/a cathode readout permanently downscoped, then…
Can fit 30-degrees of chamber readout & trigger electronics in each peripheral crate
Can send 3 muons/30o MPC
Desirability depends on simulation results for di-muon efficiency, etc.
Decision to change is permanent due to cabling of crates

18. Conclusions CSC trigger primitive electronics in advanced state
MPC - CSC Track Finder prototype system very successful
Latency no longer a problem due to 1-crate Track Finder, advance of electronics, and better firmware design
Will soon need to finalize/freeze links to other systems
CSC-DT interface
CSC-RPC link board interface
DDU readout