1. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 1
Sequential Circuits
Simple circuits with feedback
Latches
Edge-triggered flip-flops
Timing Methodologies
Cascading flip-flops for proper operation
Clock skew
Basic Registers
Shift registers
Counters
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2. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 2
Sequential Circuits
Circuits with Feedback
Outputs = f(inputs, past inputs, past outputs)
Basis for building "memory" into logic circuits
Door combination lock is an example of a sequential circuit
State is memory
State is an "output" and an "input" to combinational logic
Combination storage elements are also memory
new
equal
reset
value C1 C2 C3
mux control
multiplexer
comb. logic
comparator
state
clock
equal
open/closed
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3. Circuits with Feedback
How to control feedback?
What stops values from cycling around endlessly
X1 X2 • • • Xn
Z1 Z2 • • • Zn
switching network
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4. Simplest Circuits with Feedback
Two inverters form a static memory cell
Will hold value as long as it has power applied
How to get a new value into the memory cell?
Selectively break feedback path
Load new value into cell
"0"
"1"
"stored value"
"remember"
"load"
"data"
"stored value"
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5. Memory with Cross-coupled Gates
Cross-coupled NOR gates
Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)
Cross-coupled NAND gates
Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) R S Q Q' R S Q Q Q' S' R' R' S' Q
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6. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 6
Timing Behavior R S Q Q'
Reset
Hold
Set
Reset
Set
Race
100 R S Q \Q
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7. State Behavior of R-S latch
Truth table of R-S latch behavior
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
S R Q 0 0 hold unstable
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8. Theoretical R-S Latch Behavior
SR=10
SR=00
SR=01
SR=00
SR=10
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
SR=01
SR=10
SR=01
SR=01
SR=10
SR=11
SR=11
SR=11
State Diagram
States: possible values
Transitions: changes based on inputs
possible oscillation between states 00 and 11
SR=00
SR=00
SR=11
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9. Observed R-S Latch Behavior
Very difficult to observe R-S latch in the 1-1 state
One of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
Or non-deterministic transition
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
SR=10
SR=01
SR=00
SR=11
SR=00
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10. R-S Latch Analysis Break feedback path Q(t) R Q Q(t+) S Q' R S
S R Q(t) Q(t+) X X
hold
reset
set
not allowed
0 0
1 0
X 1
Q(t) R S
characteristic equation
Q(t+) = S + R’ Q(t)
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11. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 11
Gated R-S Latch
Control when R and S inputs matter
Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored
enable' S' Q' Q R' R S
Set
Reset S' R'
enable' Q Q'
100
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12. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 12
Clocks
Used to keep time
Wait long enough for inputs (R' and S') to settle
Then allow to have effect on value stored
Clocks are regular periodic signals
Period (time between ticks)
Duty-cycle (time clock is high between ticks - expressed as % of period)
duty cycle (in this case, 50%)
period
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13. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 13
Clocks (cont’d)
Controlling an R-S latch with a clock
Can't let R and S change while clock is active (allowing R and S to pass)
Only have half of clock period for signal changes to propagate
Signals must be stable for the other half of clock period
clock' S' Q' Q R' R S
clock
R' and S'
changing
stable
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14. Edge-Triggered Flip-Flops
More efficient solution: only 6 gates
sensitive to inputs only near edge of clock signal (not while high) Q D
Clk=1 R S D’ Q’
holds D' when
clock goes low
negative edge-triggered D flip-flop (D-FF)
4-5 gate delays
must respect setup and hold time constraints to successfully capture input
holds D when clock goes low
characteristic equation Q(t+1) = D
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15. Edge-Triggered Flip-Flops (cont’d)
Step-by-step analysis Q D
Clk=0 R S D’ Q
new D
Clk=0 R S D D’
new D  old D
when clock goes high-to-low
data is latched
when clock is low
data is held
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16. Edge-Triggered Flip-Flops (cont’d)
D = 0, Clk High 1
Act as inverters D’ D D’
Hold state R Q
Clk=1 1 S D D’ D
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17. Edge-Triggered Flip-Flops (cont’d)
D = 1, Clk High 1
1 ® 0
0 ® 1 D’ D D’ R Q
Clk=1 1 S D
0 ® 1 D’ D 1
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18. Edge-Triggered Flip-Flops (cont’d)
D = 1, Clk LOW 1
Act as inverters D’ D D’
0 ® 1 R Q
Clk=0
1 ® 0 1 S
0 ® 1 D 1 D’ D
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19. Edge-Triggered Flip-Flops (cont’d)
Positive edge-triggered
Inputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flops
Inputs sampled on falling edge; outputs change after falling edge
100 D
CLK
Qpos
Qpos'
Qneg
Qneg'
positive edge-triggered FF
negative edge-triggered FF
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20. Negative Edge Trigger FF in Verilog
module d_ff (q, q_bar, data, clk);
input data, clk;
output q, q_bar;
reg q;
assign q_bar = ~q;
clk)
begin
q <= data;
end
endmodule
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21. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 35
Registers
Collections of flip-flops with similar controls and logic
Stored values somehow related (e.g., form binary value)
Share clock, reset, and set lines
Similar logic at each stage
Examples
Shift registers
Counters R S D Q
OUT1
OUT2
OUT3
OUT4
CLK
IN1
IN2
IN3
IN4
"0"
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22. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 36
Shift Register
Holds samples of input
Store last 4 input values in sequence
4-bit shift register: D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
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23. Shift Register Verilog
module shift_reg (out4, out3, out2, out1, in, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;
clk)
begin
out4 <= out3;
out3 <= out2;
out2 <= out1;
out1 <= in;
end
endmodule
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24. Shift Register Verilog
module shift_reg (out, in, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;
clk)
begin
out <= {out[3:1], in};
end
endmodule
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25. Universal Shift Register
Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Shift in new values from left or right
left_in
left_out
right_out
clear
right_in
output
input s0 s1
clock
clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function hold state shift right shift left load new input
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26. Design of Universal Shift Register
Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th cell
to N+1th cell Q D
CLK
clear s0 s1 new value 1 – – output output value of FF to left (shift right) output value of FF to right (shift left) input
CLEAR
s0 and s1 control mux 1 2 3
Q[N-1] (left)
Q[N+1] (right)
Input[N]
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27. Universal Shift Register Verilog
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg [3:0] out;
assign lo = out[3];
assign ro = out[0];
clk or clr)
begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
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28. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 44
Counters
Sequences through a fixed set of patterns
In this case, 1000, 0100, 0010, 0001
If one of the patterns is its initial state (by loading or set/reset)
Mobius (or Johnson) counter
In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 D Q IN
OUT1
OUT2
OUT3
OUT4
CLK D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
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29. CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 45
Binary Counter
Logic between registers (not just multiplexer)
XOR decides when bit should be toggled
Always for low-order bit, only when first bit is true for second bit, and so on D Q
OUT1
OUT2
OUT3
OUT4
CLK
"1"
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30. Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;
clk)
begin
out4 <= (out1 & out2 & out3) ^ out4;
out3 <= (out1 & out2) ^ out3;
out2 <= out1 ^ out2;
out1 <= out1 ^ 1b’1;
end
endmodule
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31. Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;
clk)
out <= out + 1;
endmodule
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32. Sequential Logic Summary
Fundamental building block of circuits with state
Latch and flip-flop
R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
Timing methodologies
Use of clocks
Cascaded FFs work because prop delays exceed hold times
Beware of clock skew
Basic registers
Shift registers
Pattern detectors
Counters
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