1. DSP56800E System Architecture
Introduction to 5685x Series
Monday, November 12, 2018

2. Program and Data Memories
Introduction to 5685x Series
Monday, November 12, 2018

3. DSP56800E Core Architecture
Introduction to 5685x Series
Monday, November 12, 2018

4. DSP56800E General Purpose Registers
Introduction to 5685x Series
Monday, November 12, 2018

5. Registers with dedicated Functionalities
Introduction to 5685x Series
Monday, November 12, 2018

6. Introduction to 5685x Series
Data Type
Integer Types:
Byte (8-bit)
Word (16-bit)
Long Word (32-bit)
Fractional Data Types
Word
Long Word
Word 15 S S . .
Upper Byte
Lower Byte
Long Word 31
0x000A
0x000B
Least Significant Portion (LSP)
Most Significant Portion (MSP) S .
MSP
LSP
16-bit
Introduction to 5685x Series
Monday, November 12, 2018

7. Introduction to 5685x Series
Data Formats
Signed Integer
Unsigned Integer
Signed Fractional
Unsigned Fractional
Byte (N = 8)
Word (N =16)
Long Word (N = 32)
Introduction to 5685x Series
Monday, November 12, 2018

8. Introduction to 5685x Series
Integer Vs Fractional
Fractional Value = Integer Value/215
Introduction to 5685x Series
Monday, November 12, 2018

9. Introduction to 5685x Series
DSP56800E Core Components
Address Buses
Data Buses
Data Arithmetic Logic Unit (ALU)
Address Generation Unit (AGU)
Program Controller
Bit Manipulation Unit
Enhanced OnCE(Onchip Emulation) Debugging Module
Introduction to 5685x Series
Monday, November 12, 2018

10. Introduction to 5685x Series
Address and Data Buses
Three Address Buses:
Program memory Address Bus (PAB) – 21 bit
Primary Data Address Bus (XAB1) – 24 bit
Secondary Data Address Bus (XAB2) – 24 bit
Data Buses
Data transfers inside the chip occur over the following buses:
Two unidirectional 32-bit buses:
Core Data Bus for Reads (CDBR)
Core Data Bus for Writes (CDBW)
Two unidirectional 16-bit buses:
Secondary X Data Bus (XDB2)
Program Data Bus (PDB)
IPBus interface
XAB1 bus can address byte, word, and long data types. The XAB2 bus is limited to
(16-bit) word accesses.
Introduction to 5685x Series
Monday, November 12, 2018

11. Introduction to 5685x Series
DSP56800E Core Components
Address Buses
Data Buses
Address Generation Unit (AGU)
Data Arithmetic Logic Unit (ALU)
Program Controller
Bit Manipulation Unit
Enhanced OnCE(Onchip Emulation) Debugging Module
Introduction to 5685x Series
Monday, November 12, 2018

12. DSP56800E Core Architecture
Introduction to 5685x Series
Monday, November 12, 2018

13. Arithmetic Logic Unit (ALU)
Introduction to 5685x Series
Monday, November 12, 2018

14. Introduction to 5685x Series
Data ALU Block Diagram
Introduction to 5685x Series
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15. Introduction to 5685x Series
Data ALU Components
Three 16-bit data registers (X0, Y0, and Y1)
Four 36-bit accumulator registers (A, B, C, and D)
A single-cycle multiply-accumulator (MAC) unit
A single-bit accumulator shifter
An arithmetic and logical multi-bit shifter
A MAC output limiter
A data limiter
Introduction to 5685x Series
Monday, November 12, 2018

16. Introduction to 5685x Series
Data Registers (X0, Y1, Y0)
There are three independent 16-bit registers—X0, Y1, and Y0 serving as data registers for operations in the data ALU. The 16-bit Y1 register and the 16-bit Y0 register can be concatenated together to form a 32-bit register called Y.
Introduction to 5685x Series
Monday, November 12, 2018

17. Accumulator Registers (A, B, C,D)
The data ALU contains four, independent, 36-bit accumulator registers that serve as the source or destination for operations in the data ALU.
Each 36-bit data ALU accumulator register is composed of three different portions:
• 4-bit extension register, FF2 (where FF2 represents A2, B2, C2, or D2)
• 16-bit most significant product (MSP), FF1 (where FF1 represents A1, B1, C1, or D1)
• 16-bit least significant product (LSP), FF0 (where FF0 represents A0, B0, C0, or D0)
Introduction to 5685x Series
Monday, November 12, 2018

18. Introduction to 5685x Series
16-bit Multiplication
Signed Multiplication: N Bits x N Bits = (2N – 1) Bits
Introduction to 5685x Series
Monday, November 12, 2018

19. Introduction to 5685x Series
16-bit Multiplication
Introduction to 5685x Series
Monday, November 12, 2018

20. Introduction to 5685x Series
16-bit Multiplication
Signed Fractional Multiplication – Result stored in Accumulator
Note: If MPYR, intermediate result rounded to 16 bits, and the LSP is cleared.
Introduction to 5685x Series
Monday, November 12, 2018

21. Introduction to 5685x Series
16-bit Multiplication
Signed Integer Multiplication – Result stored in Accumulator
Introduction to 5685x Series
Monday, November 12, 2018

22. Introduction to 5685x Series
16-bit Multiplication
Signed Word-Size Integer Multiplication – Result stored in
Accumulator
IMPY.W generates directly a 16-bit result without the need for rounding.
Introduction to 5685x Series
Monday, November 12, 2018

23. Fractional Multiplication 16x32 bits
Introduction to 5685x Series
Monday, November 12, 2018

24. Shifting 32-Bit Long Words
Introduction to 5685x Series
Monday, November 12, 2018

25. Introduction to 5685x Series
Normalization
Only MSP shifted and the LSP is cleared
Introduction to 5685x Series
Monday, November 12, 2018

26. Saturation Mechanisms
Introduction to 5685x Series
Monday, November 12, 2018

27. Introduction to 5685x Series
DSP56800E Core Components
Address Buses
Data Buses
Address Generation Unit (AGU)
Data Arithmetic Logic Unit (ALU)
Program Controller
Bit Manipulation Unit
Enhanced OnCE(Onchip Emulation) Debugging Module
Introduction to 5685x Series
Monday, November 12, 2018

28. DSP56800E Core Architecture
Introduction to 5685x Series
Monday, November 12, 2018

29. Introduction to 5685x Series
AGU Block Diagram
Provides up to 2 Data Memory Addresses per cycle
Performs up to 2 Address Calculations after Issuing Addresses
Introduction to 5685x Series
Monday, November 12, 2018

30. Introduction to 5685x Series
AGU Components
A 24-bit primary address arithmetic unit
Used for AGU arithmetic instructions
Complex operand effective addresses are calculated using either linear or modulo arithmetic.
A 24-bit secondary address adder unit
Used for address updates on the R3 register used for parallel move instructions.
Performs only linear arithmetic
Single bit shifting units
Used to support byte addressing
Introduction to 5685x Series
Monday, November 12, 2018

31. Introduction to 5685x Series
AGU Programming Model
Six 24-bit address registers (R0–R5)
A 24-bit stack pointer register (SP)
A 24-bit offset register (N, which may also be used as an address register)
A 16-bit offset register (N3)
A 16-bit modifier register (M01)
Four shadow registers (shadows of R0, R1, N, and M01)
Introduction to 5685x Series
Monday, November 12, 2018

32. AGU Registers Description
Address registers (R0-R5, N)
Used typically as pointers to memory
Offset register N can also be used as address register
Stack pointer (SP)
Used to access the software stack
Register not initialized at reset
Application need to establish stack base address
Offset Register (N)
Used for indexed and post update addressing modes
Secondary read offset register (N3)
Used for post updating the R3 pointer register in dual read instructions
Modifier register (M01)
Specifies whether linear or modulo arithmetic is used
Has only effects on R0 and R1
Shadow registers
Four shadow registers corresponding to R0, R1, N and MO1
Not directly accessible
Available when using “SWAP” instruction”
Used in fast interrupt
Introduction to 5685x Series
Monday, November 12, 2018

33. Introduction to 5685x Series
DSP56800E Core Components
Address Buses
Data Buses
Address Generation Unit (AGU)
Data Arithmetic Logic Unit (ALU)
Program Controller
Bit Manipulation Unit
Enhanced OnCE(Onchip Emulation) Debugging Module
Introduction to 5685x Series
Monday, November 12, 2018

34. DSP56800E Core Architecture
Introduction to 5685x Series
Monday, November 12, 2018

35. Program Controller Block Diagram
Introduction to 5685x Series
Monday, November 12, 2018

36. Program Controller Architecture
Instruction latch and decode
Program counter (PC)
Hardware stack
Looping control unit
Interrupt control unit
Interrupt arbitration unit
Introduction to 5685x Series
Monday, November 12, 2018

37. Program Controller Programming Model
Status register (SR)
Operating mode register (OMR)
Hardware stack register (HWS)
Two loop address registers (LA and LA2)
Two loop count registers (LC and LC2)
Fast interrupt return address register (FIRA)
Fast interrupt status register (FISR)
Introduction to 5685x Series
Monday, November 12, 2018

38. Operating Mode Register
Used to configure the memory map and the operation of the data ALU
When a bit of the OMR is changed by an instruction, a delay of 2 instruction cycles is necessary before the new mode comes into effect.
When individual bits in the OMR are modified, the BFCLR, BFCHG, or BFSET instructions should be used instead of a MOVE instruction to prevent the accidental modification of other bits.
Introduction to 5685x Series
Monday, November 12, 2018

39. Introduction to 5685x Series
Status Register
The status register (SR) is a 16-bit register that consists of an 8-bit mode register (MR) and an 8-bit condition code register (CCR). MR occupies the high-order 8 bits of the SR; CCR occupies the low-order 8 bits.
The mode register reflects and defines the operating state of the DSP core, including the current interrupt priority level. The condition code register reflects various properties of the values that result from instruction execution.
Introduction to 5685x Series
Monday, November 12, 2018

40. Introduction to 5685x Series
Loop Registers
Loop Count (LC)
Specifies the number of times to repeat the hardware loop (DO,DOSLC, REP instructions)
At the end of each loop the register LC is tested to check if it is zero to exit the loop
LC register is updated with the contents of LC2 when loop is exited
Loop Count 2 (LC2)
Used to save the value of LC whenever LC is changed
Useful for nested hardware loops
Loop Address (LA)
Holds the location of the last instruction word in a hardware DO loop
Used to determine the end of a loop
Loop Address (LA2)
Used to save the value of LA when a DO loop is nested within another DO loop
Introduction to 5685x Series
Monday, November 12, 2018

41. Fast Interrupt Registers
Critical bits from OMR and SR are copied to Fast Interrupt Status Register (FISR) during fast interrupt
Fast Interrupt Return Address (FIRA) is a 21-bit register holding a copy of the program counter when fast interrupt is initiated
Introduction to 5685x Series
Monday, November 12, 2018

42. Hardware Stack Register
Last-in-first-out (LIFO) stack that consists of two 2-bit internal registers
Accessed through the hardware stack regsiter (HWS)
Reads or writes to the HWS access or modify the top location of the stack
Executing a hardware loop pushes the address of the first instruction to the stack
Introduction to 5685x Series
Monday, November 12, 2018

43. Introduction to 5685x Series
Hardware Loop
Special looping hardware
Two Types:
Fast repetition of a single instruction a specified number of times (REP instruction)
Traditional multi instruction loops using DO and DOSLC
DO instruction allows an immediate value up to 63 to be specified
For values larger than 63, DOSLC should be used with LC loaded prior with the number or repetition times
Introduction to 5685x Series
Monday, November 12, 2018

44. Dependencies with Hardware Looping
A dependency occurs when the LC register is loaded prior to executing one of the hardware looping instructions.
Due to the architecture of the instruction pipeline, none of the hardware looping instructions can be executed immediately after a value is placed in the LC register.
MOVEU.W R0,LC ;
DOSLC LABEL ;
MOVE.W X:(R3)+,X0 ; n3
ADD X0,B ; n4
LABEL
The solution to this problem is to insert instructions that require at least 2 cycles to execute between the
load of LC and the DOSLC instruction.
Introduction to 5685x Series
Monday, November 12, 2018

45. Introduction to 5685x Series
Memory Stack
Software Stack support for structured programming
Supports Local Variables stored through PUSH and retrieved using POP
Supports Parameter Passing to a Function
For both C and Assembly Code
Utilizes strong set of SP
Addressing Modes
Introduction to 5685x Series
Monday, November 12, 2018

46. Introduction to 5685x Series
DSP56800E Core Components
Address Buses
Data Buses
Address Generation Unit (AGU)
Data Arithmetic Logic Unit (ALU)
Program Controller
Bit Manipulation Unit
Enhanced OnCE(Onchip Emulation) Debugging Module
Introduction to 5685x Series
Monday, November 12, 2018

47. DSP56800E Core Architecture
Introduction to 5685x Series
Monday, November 12, 2018

48. Introduction to 5685x Series
Bit Manipulation Unit
Introduction to 5685x Series
Monday, November 12, 2018

49. Bit Manipulation Unit Capabilities
Strong Set of Bit Manipulation
Instructions:
BFSET: Test and then set a field of bits in a word
BFCLR: Test and then clear a field of bits in a word
BFCHG: Test and then invert a field of bits in a word
BFTSTH: Test a field of bits for all "1"s
BFTSTL: Test a field of bits for all "0"s
BRSET: Branch if a selected set of bits are all "1"s
BRCLR: Branch if a selected set of bits are all "0"s
Operates on any register or data memory location on the chip
Bit Manipulation Instructions Performed Only in Data ALU:
16-Bit Bidirectional Multi-bit Shifting (uses Data ALU registers)
Arithmetic and Logical Shifts (uses Data ALU registers)
Rotates (uses Data ALU registers)
Increment and Decrement of Memory Locations
Introduction to 5685x Series
Monday, November 12, 2018

50. Introduction to 5685x Series
DSP56800E Core Components
Address Buses
Data Buses
Address Generation Unit (AGU)
Data Arithmetic Logic Unit (ALU)
Program Controller
Bit Manipulation Unit
Enhanced OnCE(Onchip Emulation) Debugging Module
Introduction to 5685x Series
Monday, November 12, 2018

51. DSP56800E Core Architecture
Introduction to 5685x Series
Monday, November 12, 2018

52. Introduction to 5685x Series
Core JTAG / EOnCE TAP
Notation:
JTAG: Joint Test Action Group
EOnCE: Enhanced On-Chip Emulation
TAP: Test Access Port (also known as JTAG port)
The EOnCE and TAP work together to provide integrated support for application software development and real-time debugging.
The EOnCE module allows non-intrusive interaction with the DSP and is accessible through the pins of the JTAG interface (using the JTAG access protocol) or by software program control of the DSP56800E core.
Introduction to 5685x Series
Monday, November 12, 2018

53. Core JTAG / EOnCE Interface Diagram
Introduction to 5685x Series
Monday, November 12, 2018

54. Enhanced OnCE Module Capabilities
Examine or modify the contents of any core or memory-mapped peripheral register
Examine and modify program or data memory
Save a programmable change-of-flow instruction capture to the trace buffer
Display the contents of the real-time instruction trace buffer
Allow the transfer of data between the core and external host in real-time program execution by using peripheral-mapped transmit and receive registers
Access Enhanced OnCE registers and programming model by either the DSP56800E software or the debugging system through the JTAG port
Provide status of Enhanced OnCE events in a status register or on an output pin from the core
Count a variety of events including clock cycles and instructions executed
Interrupt or break into debug mode on program memory addresses (fetch, read, write, or read and write access)
Introduction to 5685x Series
Monday, November 12, 2018