1. 触发器 刘鹏 liupeng@zju.edu.cn 浙江大学信息与电子工程系 March 8, 2012 EE141
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2. 复习 本节内容 组合电路和Verilog语言 补充测试 时序电路的基本概念 触发器
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3. 测试（补充） 测试模块的HDL格式： 测试是一个专门用来给电路的HDL模型施加的一个激励的HDL程序，目的是测试和观察其在激励下的响应。
典型的测试模块没有输入和输出，加到设计模块用于模拟的输入信号在激励模块中定义为局部reg型数据。显示设计模块的测试输出在激励模块中定义为局部wire型数据。用局部的标识来例化测试的模块。
测试模块的HDL格式：
module test_module_name;
//Declare local reg and wire identifiers.
//Instantiate the design module under test.
//Specify a stopwatch, using $finish to terminate the simulation
//Generate stimulus, using initial and always statements.
//Display the output response (text or graphics (or both)).
endmodule
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4. Sequential Logic 时序逻辑 Sequential Circuits 时序电路 Timing Methodologies定时
EE141
Sequential Logic 时序逻辑
Sequential Circuits 时序电路
Simple circuits with feedback
Latches (level sensitive)
Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches.
Flip-flops (edge sensitive)
A flip-flop is a binary storage device capable of storing one bit of information.
Timing Methodologies定时
Cascading级联 flip-flops for proper operation
Clock skew时钟偏移
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5. Sequential Circuits Circuits with Feedback
Outputs = f(inputs, past inputs, past outputs)
Basis for building "memory" into logic circuits
Door combination lock is an example of a sequential circuit
State is memory
State is an "output" and an "input" to combinational logic
Combination storage elements are also memory
new
equal
reset
value C1 C2 C3
mux control
multiplexer
comb. logic
comparator
state
clock
equal
open/closed
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6. Circuits with Feedback
How to control feedback?
What stops values from cycling around endlessly
X1 X2 • • • Xn
Z1 Z2 • • • Zn
switching network
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7. Simplest Circuits with Feedback
Two inverters form a static memory cell
Will hold value as long as it has power applied
How to get a new value into the memory cell?
Selectively break feedback path
Load new value into cell
"0"
"1"
"stored value"
"remember"
"load"
"data"
"stored value"
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8. Memory with Cross-coupled Gates
EE141
Memory with Cross-coupled Gates
Cross-coupled NOR gates
Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)
Cross-coupled NAND gates
Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) R S Q Q' R S Q Q Q' S' R' R' S' Q
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9. Timing Behavior R S Q Q' Reset Hold Set Reset Set Race 100 R S Q \Q
EE141
Timing Behavior R S Q Q'
Reset
Hold
Set
Reset
Set
Race
100 R S Q \Q
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10. State Behavior of R-S latch
EE141
State Behavior of R-S latch
Truth table of R-S latch behavior
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
S R Q 0 0 hold unstable
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11. Theoretical R-S Latch Behavior
EE141
Theoretical R-S Latch Behavior
SR=10
SR=00
SR=01
SR=00
SR=10
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
SR=01
SR=10
SR=01
SR=01
SR=10
SR=11
SR=11
SR=11
State Diagram
States: possible values
Transitions: changes based on inputs
possible oscillation between states 00 and 11
SR=00
SR=00
SR=11
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12. Observed R-S Latch Behavior
EE141
Observed R-S Latch Behavior
Very difficult to observe R-S latch in the 1-1 state
One of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
Or non-deterministic transition
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
SR=10
SR=01
SR=00
SR=11
SR=00
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13. characteristic equation
EE141
R-S Latch Analysis
Break feedback path R S Q Q'
Q(t)
Q(t+) S R
S R Q(t) Q(t+) X X
hold
reset
set
not allowed
0 0
1 0
X 1
Q(t) R S
characteristic equation
Q(t+) = S + R’ Q(t)
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14. Gated R-S Latch Control when R and S inputs matter
EE141
Gated R-S Latch
Control when R and S inputs matter
Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored
enable' S' Q' Q R' R S
Set
Reset S' R'
enable' Q Q'
100
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15. Clocks Used to keep time Clocks are regular periodic signals
Wait long enough for inputs (R' and S') to settle
Then allow to have effect on value stored
Clocks are regular periodic signals
Period (time between ticks)
Duty-cycle (time clock is high between ticks - expressed as % of period)
duty cycle (in this case, 50%)
period
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16. Clocks (cont’d) Controlling an R-S latch with a clock
EE141
Clocks (cont’d)
Controlling an R-S latch with a clock
Can't let R and S change while clock is active (allowing R and S to pass)
Only have half of clock period for signal changes to propagate
Signals must be stable for the other half of clock period
clock' S' Q' Q R' R S
clock
R' and S'
changing
stable
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17. Cascading Latches Connect output of one latch to input of another
EE141
Cascading Latches
Connect output of one latch to input of another
How to stop changes from racing through chain?
Need to control flow of data from one latch to the next
Advance from one latch per clock period
Worry about logic between latches (arrows) that is too fast
clock R S Q Q'
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18. Master-Slave Structure
EE141
Master-Slave Structure
Break flow by alternating clocks (like an air-lock)
Use positive clock to latch inputs into one R-S latch
Use negative clock to change outputs with another R-S latch
View pair as one basic unit
master-slave flip-flop
twice as much logic
output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops
master stage
slave stage P P'
CLK R S Q Q'
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19. The 1s Catching Problem In first R-S stage of master-slave FF
EE141
The 1s Catching Problem
In first R-S stage of master-slave FF
0-1-0 glitch on R or S while clock is high "caught" by master stage
Leads to constraints on logic to be hazard-free
master stage
slave stage P P'
CLK R S Q Q'
Set
1s catch S R
CLK P P' Q Q'
Reset
Master Outputs
Slave Outputs
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20. D Flip-Flop Make S and R complements of each other
EE141
D Flip-Flop
Make S and R complements of each other
Eliminates 1s catching problem
Can't just hold previous value (must have new value ready every clock period)
Value of D just before clock goes low is what is stored in flip-flop
Can make R-S flip-flop by adding logic to make D = S + R' Q D Q Q'
master stage
slave stage P P'
CLK R S
10 gates
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21. 提高可靠性，要求每个CLK周期输出状态只能改变1次
EE141
脉冲触发的触发器
提高可靠性，要求每个CLK周期输出状态只能改变1次
一、电路结构与工作原理
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22. EE141 X 1 1*
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23. EE141 J K Q’ 主 从 S R Q
CLK
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24. EE141 J 主 从 S R K Q Q’
CLK
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25. (5) 列出真值表 主 从 S R J K Q Q’ CLK X X 1 1 1* EE1411 X 1 1* 主 从 S R J K Q Q’
CLK
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26. 二、脉冲触发方式的动作特点 主 从 S R J K Q Q’ CLK EE141
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27. EE141
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28. 课后作业 习题：/P248 Verilog HDL语言 自学 阅读： 5.2, 5.3, 5.4,5.6,5.9, ch6.1-6.3;
EE141
课后作业
习题：/P248
5.2, 5.3, 5.4,5.6,5.9,
Verilog HDL语言 自学
阅读：
ch ;
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