1. CCD Devices Contents: Capacitance How they work Resolution
Magnification

2. Concept 0 - Capacitance C = q V C = capacitance (Farads)
q = Charge on the capacitor (C)
V = voltage across the capacitor (V)
demo big cap
A CCD pixel has a capacitance of 1.7x10-12 F. What is the voltage across it if it has been charged 6.0x104 electron charges? (1 e = 1.602E-19)
V = q/C = (6.0E11*1.602E-19/1.7E-16) = 5.7 mV
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3. Whiteboards:
Capacitance
1 | 2 | 3
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4. What is the charge on a 250 microfarad capacitor if it has been charged to 12 V?
q = CV = (250E-6 F)(12 V) = 3E-3 Coulombs W
.0030 C

5. What is the capacitance of a CCD pixel if it has
What is the capacitance of a CCD pixel if it has .014 V across it when it has a charge of 2.13x10-15 C?
C = q/V = (2.13E-15 C)/(.014 V) = 1.52x10-13 F W
1.52x10-13 F

6. Example: A 3. 1x10-10 m2 CCD pixel has a capacitance of 2
Example: A 3.1x10-10 m2 CCD pixel has a capacitance of 2.3 pF (x10-12) If after being exposed to light, it has picked up a charge of 3.45x10-14 C, what is the voltage across it? How many electrons were displaced from the pixel? If photons displaced these electrons, then what is the photon flux in photons/m2 incident on the CCD?
(e = 1.602E-19 C/electron)
V = q/C = (3.45E-14C )/(2.3E-12 F) = .015 V
# electrons = (3.45E-14C )/(1.602E-19 C/electron) = 2.154E5 electrons
photons/m2 = (2.154E5 electrons)/(3.1E-10 m2) = 6.95E14 photons/m2
A sunny day = about 1000 W/m2 ≈ 3x1021 photons/sec (550 nm)
(a force of 3.3x10-6 N/m2 W
0.015 V E5 electrons E14 photons/m2

7. How a CCD Works (Charge-Coupled Device)
Photons charge electrodes
Voltages from pixels is shifted off the chip
The voltage is converted to digital
Charge-coupled devices (CCDs) are silicon-based integrated circuits consisting of a dense matrix of photodiodes that operate by converting light energy in the form of photons into an electronic charge. Electrons generated by the interaction of photons with silicon atoms are stored in a potential well and can subsequently be transferred across the chip through registers and output to an amplifier. The schematic diagram illustrated in Figure 1 shows various components that comprise the anatomy of a typical CCD.
CCDs were invented in the late 1960's by research scientists at Bell Laboratories, who initially conceived the idea as a new type of memory circuit for computers. Later studies indicated that the device, because of its ability to transfer charge and the photoelectric interaction with light, would also be useful for other applications such as signal processing and imaging. Early hopes of a new memory device have all but disappeared, but the CCD is emerging as one of the leading candidates for an all-purpose electronic imaging detector, capable of replacing film in the emerging field of digital photomicrography.
Fabricated on silicon wafers much like integrated circuits, CCDs are processed in a series of complex photolithographic steps that involve etching, ion implantation, thin film deposition, metallization, and passivation to define various functions within the device. The silicon substrate is electrically doped to form p-type silicon, a material in which the main carriers are positively charged electron holes. Multiple dies, each capable of yielding a working device, are fabricated on each wafer before being cut with a diamond saw, tested, and packaged into a ceramic or polymer casing with a glass or quartz window through which light can pass to illuminate the photodiode array on the CCD surface. Explore the sequence of steps necessary to build a CCD using our interactive Java tutorial, which is linked from the dialog box.
Interactive Java Tutorial
Building A Charge-Coupled Device
Explore the steps utilized in the construction of a charge-coupled device (CCD) as a portion of an individual pixel gate is fabricated on a silicon wafer simultaneously with thousands or even millions of neighboring elements.
When a ultraviolet, visible, or infrared photon strikes a silicon atom resting in or near a CCD photodiode, it will usually produce a free electron and a "hole" created by the temporary absence of the electron in the silicon crystalline lattice. The free electron is then collected in a potential well (located deep within the silicon in an area known as the depletion layer), while the hole is forced away from the well and eventually is displaced into the silicon substrate. Individual photodiodes are isolated electrically from their neighbors by a channel stop, which is formed by diffusing boron ions through a mask into the p-type silicon substrate.
The principal architectural feature of a CCD is a vast array of serial shift registers constructed with a vertically stacked conductive layer of doped polysilicon separated from a silicon semiconductor substrate by an insulating thin film of silicon dioxide (see Figure 2). After electrons have been collected within each photodiode of the array, a voltage potential is applied to the polysilicon electrode layers (termed gates) to change the electrostatic potential of the underlying silicon. The silicon substrate positioned directly beneath the gate electrode then becomes a potential well capable of collecting locally-generated electrons created by the incident light. Neighboring gates help to confine electrons within the potential well by forming zones of higher potentials, termed barriers, surrounding the well. By modulating the voltage applied to polysilicon gates, they can be biased to either form a potential well or a barrier to the integrated charge collected by the photodiode.
The most common CCD designs have a series of gate elements that subdivide each pixel into thirds by three potential wells oriented in a horizontal row. Each photodiode potential well is capable of holding a number of electrons that determines the upper limit of the dynamic range of the CCD. After being illuminated by incoming photons during a period termed integration, potential wells in the CCD photodiode array become filled with electrons produced in the depletion layer of the silicon substrate. Measurement of this stored charge is accomplished by a combination of serial and parallel transfers of the accumulated charge to a single output node at the edge of the chip. The speed of parallel charge transfer is usually sufficient to be accomplished during the period of charge integration for the next image.
After being collected in the potential wells, electrons are shifted in parallel, one row at a time, by a signal generated from the vertical shift register clock. The electrons are transferred across each photodiode in a multi-step process (ranging from two to four steps). This shift is accomplished by changing the potential of the holding well negative, while simultaneously increasing the bias of the next electrode to a positive value. The vertical shift register clock operates in cycles to change the voltages on alternate electrodes of the vertical gates in order to move the accumulated charge across the CCD. Figure 1 illustrates a photodiode potential well adjacent to a transfer gate positioned within a row of CCD gates.
Four-Phase CCD Clocking Scheme
Explore how charge transfer occurs from the shift registers to the output node in a four-phase charge-coupled device clocking scheme.
After traversing the array of parallel shift register gates, the charge eventually reaches a specialized row of gates known as the serial shift register. Here, the packets of electrons representing each pixel are shifted horizontally in sequence, under the control of a horizontal shift register clock, toward an output amplifier and off the chip. The entire contents of the horizontal shift register are transferred to the output node prior to being loaded with the next row of charge packets from the parallel register. In the output amplifier, electron packets register the amount of charge produced by successive photodiodes from left to right in a single row starting with the first row and proceeding to the last. This produces an analog raster scan of the photo-generated charge from the entire two-dimensional array of photodiode sensor elements.
There are a variety of CCD elements and designs that are discussed in other sections featured in our review of Concepts in Digital Imaging Technology. These include several architectural motifs, antiblooming electron drains, microlens arrays, pixel binning, clocking schemes, scanning formats, and other topics necessary for a basic understanding of charge-coupled device theory and operation.
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8. How a CCD Works
CCDs only register light, color is achieved using filters
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9. jpeg
compression
photon
memory card

11. Resolution, sensor size and magnification
Nikon D3x: (CMOS)
Sensor size = 35.9x24.0 mm = mm2
6048x4032 resolution = 24 Mega pixels
Human eye: (rods and cones)
Sensor size = 1100 mm2
11,000x11,000 = 121 Mega Pixels
Magnification:
image/object ratio
Nikon D3x
CMOS = Complimentary Metal-Oxide Semiconductor
Low energy/higher noise/less mature technology/digital output/less light sensitivity/can access only a portion of chip if necessary
CCD = Charge-Coupled Device
100x more power/lower noise/more mature technology/more light sensitivity
The gap is closing between.
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12. Resolution, sensor size and magnification
Nikon D3x: (CMOS)
Sensor size = 35.9x24.0 mm = mm2
6048x4032 resolution = 24 Mega pixels
(Let’s assume a quantum efficiency of 70%)
A) What is the area of each pixel?
B) If light with a photon flux of 4.5x1019 photons/m2/s is incident on the sensor for 1/250th of a second, what is the resulting charge on the pixel?
C) If the voltage across the pixel is 2.4 mV, what is the capacitance of the pixel?
D) If I am 183 cm tall, and my image on the sensor is 19.2 mm tall, what is the “magnification” in this case?
CMOS = Complimentary Metal-Oxide Semiconductor
Low energy/higher noise/less mature technology/digital output/less light sensitivity/can access only a portion of chip if necessary
CCD = Charge-Coupled Device
100x more power/lower noise/more mature technology/more light sensitivity
The gap is closing between.
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13. TOC Nikon D3x: (CMOS) Sensor size = 35.9x24.0 mm = 861.6 mm2
6048x4032 resolution = 24 Mega pixels
(Let’s assume a quantum efficiency of 70%)
A) What is the area of each pixel?
total area = (35.9E-3m)x(24.0E-3) = m2
#pixels = 6048x4032 = 24,385,536 pixels
area/pixels = ( m2)/(24,385,536 pixels) = E-11 m2/pixel
B) If light with a photon flux of 4.5x1019 photons/m2/s is incident on the sensor for 1/250th of a second, what is the resulting charge on the pixel?
Photons per pixel resulting in charge =
(0.70)(4.5x1019 photons/m2/s)(1 s/250)( E-11 m2/pixel) =
e charges per pixel
So this is ( )(1.602E-19) = E-13 C
C) If the voltage across the pixel is 2.4 mV, what is the capacitance of the pixel?
C = q/V = ( E-13 C)/(2.4E-3 V) = E-10 F = 297 pF
D) If I am 183 cm tall, and my image on the sensor is 19.2 mm tall, what is the “magnification” in this case?
image/object = (1.92 cm)/(183 cm) = .0105x (it’s a smallifier)
CMOS = Complimentary Metal-Oxide Semiconductor
Low energy/higher noise/less mature technology/digital output/less light sensitivity/can access only a portion of chip if necessary
CCD = Charge-Coupled Device
100x more power/lower noise/more mature technology/more light sensitivity
The gap is closing between.
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14. Whiteboards:
Random CCD Crap
1 | 2 | 3 | 4
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15. My camera has a 25. 4 mm x 58. 4 mm CCD sensor with 4. 0 Mega pixels
My camera has a 25.4 mm x 58.4 mm CCD sensor with 4.0 Mega pixels. What is the area of each pixel in square meters?
Area per pixel = (25.4E-3 m)(58.4E-3 m)/(4.0E6) = E-10 m2 W
3.7084E-10 m2

16. A pixel builds up a potential of 5. 2 mV
A pixel builds up a potential of 5.2 mV. How many photons hit it if it has a capacitance of 13 pF, and a quantum efficiency of 75%?
q = CV = (13E-12F)(5.2E-3) = 6.76E-14 C
# electrons = 421,972
#electrons/#photons = .75, #photons = (421,972)/.75 = 562,630 W
560,000 photons

17. A single pixel with an area of 3
A single pixel with an area of 3.7x10-10 m2 is hit with 562,630 photons. What is the light intensity in photons/m2?
photons/m2 = (562,630)/(3.7x10-10 m2) = 1.5E+15 W
1.5x1015 photons/m2