4. Figure 13.1 MIPS Single Clock Cycle Implementation.

5. Figure 13.2 MIPS Pipelined Implementation.

10. Figure 13.3 Block Diagram of MIPS Control Unit

13. Figure 13.4 Block Diagram of MIPS Fetch Unit.

16. Figure 13.5 MIPS Program Memory Initialization File, program.mif.

17. Figure 13.6 Block Diagram of MIPS Decode Unit.

20. Figure 13.7 Block Diagram of MIPS Execute Unit.

23. Figure 13.8 Block Diagram of MIPS Data Memory Unit.

25. Figure 13.9 MIPS Data Memory Initialization File, dmemory.mif.

26. Figure 13.10 Simulation of MIPS test program.

27. Figure 13.11 MIPS with Video Output generated by UP 1 Board.