1. Instructors: Randy H. Katz David A. Patterson
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Muxes, Adders, and ALUs
Instructors: Randy H. Katz David A. Patterson
11/12/2018
Fall Lecture #24

2. Agenda Multiplexer Administrivia Technology Break ALU Design
11/12/2018
Fall Lecture #24

3. Agenda Multiplexer Administrivia Technology Break ALU Design
11/12/2018
Fall Lecture #24

4. Data Multiplexer (e.g., 2-to-1 x n-bit-wide)
“mux”
11/12/2018
Fall Lecture #24

5. N Instances of 1-bit-Wide Mux
How many rows in TT?
11/12/2018
Fall Lecture #24

6. How Do We Build a 1-bit-Wide Mux?
11/12/2018
Fall Lecture #24

7. 4-to-1 Multiplexer How many rows in TT? 11/12/2018
Fall Lecture #24

8. Alternative Hierarchical Approach
11/12/2018
Fall Lecture #24

9. Arithmetic and Logic Unit
Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU)
We’ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR
11/12/2018
Fall Lecture #24

10. Simple ALU
11/12/2018
Fall Lecture #24

11. Agenda Mutiplexers Administrivia Technology Break ALU 11/12/2018
Fall Lecture #24

12. Agenda Mux + Adder Design Administrivia Technology Break ALU Design
11/12/2018
Fall Lecture #24

13. Agenda Multiplexer Administrivia Technology Break ALU Design
11/12/2018
Fall Lecture #24

14. Adder/Subtractor: One-bit adder Least Significant Bit
11/12/2018
Fall Lecture #24

15. Adder/Subtractor: One-bit adder (1/2) …
11/12/2018
Fall Lecture #24

16. Adder/Subtractor: One-bit Adder (2/2) …
11/12/2018
Fall Lecture #24

17. N x 1-bit Adders  1 N-bit Adder
Connect Carry Out i-1 to Carry in i: b0 +
11/12/2018
Fall Lecture #24

18. Overflow Conditions Add two positive numbers to get a negative number
or two negative numbers to get a positive number -1 +0 -1 +0 -2
1111 -2
0000 +1
1111
0000 +1
1110
1110 -3
0001 -3
0001 +2 +2
1101
1101
0010
0010 -4 -4
1100 +3
0011
1100 +3
0011 -5 -5
1011
1011
0100 +4
0100 +4
1010 -6
1010
0101 -6
0101 +5 +5
1001
1001
0110
0110 -7 +6 -7
1000 +6
0111
1000
0111 -8 +7 -8 +7
5 + 3 = -8!
= +7!
11/12/2018
Fall Lecture #24

19. Overflow Conditions 5 3 -8 -7 -2 7
Overflow
Overflow 5 2 7 -3 -5 -8
No overflow
No overflow
Overflow when carry in to sign does not equal carry out: Cn xor Cn-1
11/12/2018
Fall Lecture #24

20. Twos Complement Adder/Subtractor
11/12/2018
Fall Lecture #24

21. Design Hierarchy system datapath control code registers
state registers
combinational logic
multiplexer
comparator
register
logic
switching networks
11/12/2018
Fall Lecture #24

22. Summary Use muxes to select among input
S input bits selects 2S inputs
Each input can be n-bits wide, indep of S
Can implement muxes hierarchically
ALU can be implemented using a mux
Coupled with basic block elements
N-bit adder-subtractor done using N 1-bit adders with XOR gates on input
XOR serves as conditional inverter
11/12/2018
Fall Lecture #24