1. VLSI Arithmetic Lecture 5
Prof. Vojin G. Oklobdzija
University of California

2. Review
Lecture 4

3. Ling’s Adder Huey Ling, “High-Speed Binary Adder”
IBM Journal of Research and Development, Vol.5, No.3, 1981.
Used in: IBM 3033, IBM S370/168, Amdahl V6, HP etc.

4. Ling’s Derivations define:ai bi ci si
ci+1
define:
gi implies Ci+1 which implies Hi+1 , thus: gi= gi Hi+1 ai bi pi gi ti 1
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5. Ling’s Derivations From: Now we need to derive Sum equation and
because:
fundamental expansion
Now we need to derive Sum equation
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6. Ling Adder Ling’s equations: Variation of CLA:
Ling, IBM J. Res. Dev, 5/81
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7. Ling Adder Ling’s equation: Variation of CLA:ai bi ci si
ci+1
ai-1
bi-1
ci-1
si-1
gi, ti
gi-1, ti-1
Hi+1 Hi
Ling uses different transfer function.
Four of those functions have desired
properties (Ling’s is one of them)
see: Doran, IEEE Trans on Comp. Vol 37, No.9 Sept
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8. Ling Adder Conventional: Ling: Fan-in of 5 Fan-in of 4 Oklobdzija 2004
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9. Advantages of Ling’s Adder
Uniform loading in fan-in and fan-out
H16 contains 8 terms as compared to G16 that contains 15.
H16 can be implemented with one level of logic (in ECL), while G16 can not (with 8-way wire-OR).
(Ling’s adder takes full advantage of wired-OR, of special importance when ECL technology is used - his IBM limitation was fan-in of 4 and wire-OR of 8)
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10. Ling: Weinberger Notes
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11. Ling: Weinberger Notes
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12. Ling: Weinberger Notes
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13. Advantage of Ling’s Adder
32-bit adder used in: IBM 3033, IBM S370/ Model168, Amdahl V6.
Implements 32-bit addition in 3 levels of logic
Implements 32-bit AGEN: B+Index+Disp in 4 levels of logic (rather than 6)
5 levels of logic for 64-bit adder used in HP processor
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14. Implementation of Ling’s Adder in CMOS (S
Implementation of Ling’s Adder in CMOS (S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96)
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15. S. Naffziger, ISSCC’96
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16. S. Naffziger, ISSCC’96
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17. S. Naffziger, ISSCC’96
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18. S. Naffziger, ISSCC’96
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19. S. Naffziger, ISSCC’96
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20. S. Naffziger, ISSCC’96
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21. S. Naffziger, ISSCC’96
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22. S. Naffziger, ISSCC’96
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23. S. Naffziger, ISSCC’96
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24. S. Naffziger, ISSCC’96
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25. S. Naffziger, ISSCC’96
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26. Ling Adder Critical Path
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27. Ling Adder: Circuits
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28. LCS4 – Critical G Path
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29. LCS4 – Logical Effort Delay
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30. See: S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96
Results:
0.5u Technology
Speed: nS
Nominal process, 80C, V=3.3V
See: S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96
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31. Prefix Adders and Parallel Prefix Adders

32. from: Ercegovac-Lang
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33. Prefix Adders (g, p)o(g’,p’)=(g+pg’, pp’) (g0, p0) Gi, Pi =
Following recurrence operation is defined:
(g, p)o(g’,p’)=(g+pg’, pp’)
such that:
(g0, p0)
i=0
Gi, Pi =
(gi, pi)o(Gi-1, Pi-1 )
1 ≤ i ≤ n
ci+1 = Gi
for i=0, 1, ….. n
(g-1, p-1)=(cin,cin)
c1 = g0+ p0 cin
This operation is associative, but not commutative
It can also span a range of bits (overlapping and adjacent)
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34. from: Ercegovac-Lang
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35. Parallel Prefix Adders: variety of possibilities
from: Ercegovac-Lang
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36. Pyramid Adder: M. Lehman, “A Comparative Study of Propagation Speed-up Circuits in Binary Arithmetic Units”, IFIP Congress, Munich, Germany, 1962.
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37. Parallel Prefix Adders: variety of possibilities
from: Ercegovac-Lang
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38. Parallel Prefix Adders: variety of possibilities
from: Ercegovac-Lang
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39. Hybrid BK-KS Adder
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40. Parallel Prefix Adders: S. Knowles 1999
operation is associative: h>i≥j≥k
operation is idempotent: h>i≥j≥k
produces carry: cin=0
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41. Parallel Prefix Adders: Ladner-Fisher
Exploits associativity, but not idempotency.
Produces minimal logical depth
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42. Parallel Prefix Adders: Ladner-Fisher (16,8,4,2,1)
Two wires at each level. Uniform, fan-in of two.
Large fan-out (of 16; n/2); Large capacitive loading combined with the long wires (in the last stages)
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43. Parallel Prefix Adders: Kogge-Stone
Exploits idempotency to limit the fan-out to 1.
Dramatic increase in wires. The wire span remains the same as in Ladner-Fisher.
Buffers needed in both cases: K-S, L-F
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44. Kogge-Stone Adder
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45. Parallel Prefix Adders: Brent-Kung
Set the fan-out to one
Avoids explosion of wires (as in K-S)
Makes no sense in CMOS:
fan-out = 1 limit is arbitrary and extreme
much of the capacitive load is due to wire (anyway)
It is more efficient to insert buffers in L-F than to use B-K scheme
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46. Brent-Kung Adder
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47. Parallel Prefix Adders: Han-Carlson
Is a hybrid synthesis of L-F and K-S
Trades increase in logic depth for a reduction in fan-out:
effectively a higher-radix variant of K-S.
others do it similarly by serializing the prefix computation at the higher fan-out nodes.
Others, similarly trade the logical depth for reduction of fan-out and wire.
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48. Parallel Prefix Adders: variety of possibilities
from: Knowles
bounded by L-F and K-S at ends
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49. Parallel Prefix Adders: variety of possibilities Knowles 1999
Following rules are used:
Lateral wires at the jth level span 2j bits
Lateral fan-out at jth level is power of 2 up to 2j
Lateral fan-out at the jth level cannot exceed that a the (j+1)th level.
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50. Parallel Prefix Adders: variety of possibilities Knowles 1999
The number of minimal depth graphs of this type is given in:
at 4-bits there is only K-S and L-F, afterwards there are several new possibilities.
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51. Parallel Prefix Adders: variety of possibilities
Knowles 1999
example of a new 32-bit adder [4,4,2,2,1]
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52. Parallel Prefix Adders: variety of possibilities
Knowles 1999
Example of a new 32-bit adder [4,4,2,2,1]
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53. Parallel Prefix Adders: variety of possibilities Knowles 1999
Delay is given in terms of FO4 inverter delay: w.c.
(nominal case is 40-50% faster)
K-S is the fastest
K-S adders are wire limited (requiring 80% more area)
The difference is less than 15% between examined schemes
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54. Parallel Prefix Adders: variety of possibilities Knowles 1999
Conclusion
Irregular, hybrid schmes are possible
The speed-up of 15% is achieved at the cost of large wiring, hence area and power
Circuits close in speed to K-S are available at significantly lower wiring cost
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