1. Dr. Clincy Professor of CS
CS Chapter 3 (3A and )
Dr. Clincy
Professor of CS
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Lecture
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2. Kmap Simplification for Four Variables
Our model can be extended to accommodate the 16 minterms that are produced by a four-input function.
This is the format for a 16-minterm Kmap.
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3. Kmap Simplification Example for Four Variables
We have populated the Kmap shown below with the nonzero minterms from the function:
Reduced to:
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4. Kmap Simplification for Four Variables
It is possible to have a choice as to how to pick groups within a Kmap, while keeping the groups as large as possible.
The (different) functions that result from the groupings below are logically equivalent.
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5. Don’t Care Conditions
Real circuits don’t always need to have an output defined for every possible input.
For example, some calculator displays consist of 7- segment LEDs. These LEDs can display patterns, but only ten of them are useful.
If a circuit is designed so that a particular set of inputs can never happen, we call this set of inputs a don’t care condition.
They are very helpful to us in Kmap circuit simplification.
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6. Don’t Care Conditions
In a Kmap, a don’t care condition is identified by an X in the cell of the minterm(s) for the don’t care inputs, as shown below.
In performing the simplification, we are free to include or ignore the X’s when creating our groups.
Reduction using don’t cares:
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7. Don’t Care Example
Could have the case where some input combinations do not need to be evaluated – these input combinations are called “don’t cares”
For a k-map, use “don’t cares” in the case of creating groups of 2, 4, 8, … set of 1s – use “don’t cares as 1s to help minimize the circuit – at least one 1 has to be in a group of don’t cares

8. More Kmap Examples
When adjacent squares contain 1s, indicates the possibility of an algebraic simplication
Example of a 3-variable k-map
Inputs around edge and output in the boxes

9. Half Adder - Combinational Circuits
Combinational logic circuits give us many useful devices.
One of the simplest is the half adder, which finds the sum of two bits.
We can gain some insight as to the construction of a half adder by looking at its truth table, shown at the right.
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10. Full Adder - Combinational Circuits
We can change our half adder into to a full adder by including gates for processing the carry bit.
The truth table for a full adder is shown at the right.
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11. Adders - Combinational Circuits
Just as we combined half adders to make a full adder, full adders can be connected in series.
The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder.
Today’s systems employ more efficient adders.
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12. Decoder - Combinational Circuits
Among other things, they are useful in selecting a memory location according to a binary value placed on the address lines of a memory bus.
This is what a 2-to-4 decoder looks like on the inside.
If x = 0 and y = 1, which output line is enabled?
Output - Decoded message
Input - Encoded message
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13. Decoder – another example
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14. Multiplexer - Combinational Circuits
A multiplexer does just the opposite of a decoder.
It selects a single output from several inputs.
This is what a 4-to-1 multiplexer looks like on the inside.
Depending the “select input” combination, 1 of 4 data inputs is chosen for output
If S0 = 1 and S1 = 0, which input is transferred to the output?
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15. Multiplexer - Combinational Circuits
Can also use multiplexers to implement logic functions
Given this truth table, group X1,X2 being 00, 01, 10 and 11 – notice what happens with X3
3-input truth table can be done with a 4-input mux
4-input truth table can be done with a 8-input mux
5-input truth table can be done with a 16-input mux
Etc..
Also explain how the Mux is used to implement data comm’s FDM and TDM
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16. 10.2.2 - Programmable Logic Devices (PLD)
All possible combinations of inputs ANDed  
•••
All possible combinations of ANDed inputs ORed  
Re-explain Sums of Products and relationship to PLDs
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17. 10.2.2 - Programmable Logic Array (PLA)
Ability to program a PLD, is called a PLA
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18. 10.2.2 - Programmable Array Logic (PAL)
For a PLA, both the AND array and OR array are programmable
For a PAL, the AND array is programmable and the OR array is fixed
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19. 10.2.2 - Complex Programmable Logic Devices (CPLDs)
CPLDs are comprised of 2 or more PALs
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20. 10.2.2 - Field Programmable Gate Arrays (FPGAs)
PAL chips are somewhat limited in size due to the fact they have output pins for each sum-of-product circuit
FPGA overcome this size limitation by using a general interconnection.
General interconnection
PAL
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