1. CSCI206 - Computer Organization & Programming
Control, Forwarding, and Exceptions
zyBook: 11.9, 11.12, 11.13

2. Datapath with Forwarding
ForwardA
none 00 ? 01 10
ForwardB
none 00 ? 01 10

3. Forward Signals add r1, r1, r2 add r1, r1, r3 ForwardX none 00 MEM/WB01
EX/MEM 10
add r1, r1, r2
add r1, r1, r3
ForwardA
ForwardB

4. Forward Signal if EX/MEM.rd == ID/EX.rs ForwardA = 10
ForwardX
none 00
MEM/WB 01
EX/MEM 10
if EX/MEM.rd == ID/EX.rs
ForwardA = 10
if EX/MEM.rd == ID/EX.rt
ForwardB = 10
EX -> EX forward 1 2 3 4 5 6
add r1, r1, r2 F D E M W
add r1, r1, r3

5. Refined Forward Signal
Only check for forwarding if the previous op writes and we’re not reading the $zero register
if EX/MEM.RegWrite and EX/MEM.rd > 0
if EX/MEM.rd == ID/EX.rs
ForwardA = 10
if EX/MEM.rd == ID/EX.rt
ForwardB = 10

6. Refined Forward Signal
Only check for forwarding if the previous op writes and we’re not reading the $zero register
if MEM/WB.RegWrite and MEM/WB.rd > 0
if MEM/WB.rd == ID/EX.rs
ForwardA = 01
if MEM/WB.rd == ID/EX.rt
ForwardB = 01

7. Hazard Detection Unit

8. What happens on a stall? Hazard is detected in ID
Instruction going into EX is turned into a nop
PC register and IF/ID pipeline register are stalled
i.e., the output does not change on the next clock edge
NOP

9. Exceptions
Definition: an unscheduled event that disrupts program execution
Divide by zero is an exception
When can it be detected?
What happens?
div $t0, $t1, $zero

10. Exceptions in each stageIF
invalid PC address ID
invalid opcode (instruction) EX
arithmetic
MEM
invalid address

11. Exception Handling Rules
All instructions after the exception in the pipeline must be completed and the result committed a register or memory
Any partially executed instructions (e.g., in IF or ID) must have no effect

12. Exception Handling
Convert excepting instruction to nop and add an exception flag to the pipeline registers
Store reason for exception
Store PC of instruction that caused exception
Begin fetching at exception handler address

13. Datapath with EX exception

14. CSCI320 Topics Superpipeline (long pipelines)
Superscalar - fetch / execute multiple instructions per cycle on one datapath
Simultaneous multithreading (Hyper threading)
Superscalar design where instructions come from different threads and are executed at the same time on a single pipeline
Dynamic scheduling
The CPU reorders instructions to eliminate hazards
Multicore - data synchronization becomes difficult