1. MICRO CONTROLLER 8051
UNIT IV
Mr. S. VINOD
LECTURER
EEE DEPARTMENT

2. Functional block diagram
Instruction format
addressing modes
Interrupt structure
Timer
I/O ports
Serial communication.

3. Microprocessor vs Microcontroller
CPU is stand-alone, RAM, ROM, I/O, timer are separate
designer can decide on the amount of ROM, RAM and I/O ports.
expansive
versatility
general-purpose
Microcontroller
CPU, RAM, ROM, I/O and timer are all on a single chip
fix amount of on-chip ROM, RAM, I/O ports
for applications in which cost, power and space are critical
single-purpose
versatility 多用途的: any number of applications for PC

4. Embedded System
Embedded system means the processor is embedded into that application.
An embedded product uses a microprocessor or microcontroller to do one task only.
In an embedded system, there is only one application software that is typically burned into ROM.
Example-printer, keyboard, video game player

5. INTRODUCTION MCS-51 family, originally designed by Intel in the 1980’s
Used in a large percentage of embedded systems
Includes several on-chip peripherals, like timers and counters
128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory

6. FEATURES 8-bit CPU optimized for control applications
Extensive Boolean processing (single-bit logic) capabilities
64K Program Memory address space
64K Data Memory address space
Up to 4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
32 bi-directional and individually addressable I/O lines
Two 16-bit timer/counters
6-source/5-vector interrupt structure with two priority levels

7. Block Diagram External interrupts On-chip ROM for program code
Timer/Counter
Interrupt Control
On-chip RAM
Timer 1
Counter Inputs
Timer 0
CPU
Serial Port
Bus Control
4 I/O Ports
OSC
P0 P1 P2 P3
TxD RxD
Address/Data

8. Pin Description of the 8051 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
XTAL2
XTAL1
GND
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5

9. XTAL Connection to 8051  Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin. C2
30pF C1
XTAL2
XTAL1
GND 

11. Architecture Memory Organization Program Status Word
Interrupt Structure
Port Structures
Timer/Counters
Reset

12. Memory Organization Logical separation of program and data memory
Separate address spaces for Program (ROM) and Data (RAM) Memory
Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU
Program Memory
Only be read, not written to
The address space is 16-bit, so maximum of 64K bytes
Up to 4K bytes can be on-chip (internal) of 8051 core
PSEN (Program Store Enable) is used for access to external Program Memory

13. Memory Organization Data Memory
Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions
There is also a number of Special Function Registers (SFRs)
Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions
External memory of maximum 64K bytes is accessible by “movx”

14. Memory Organization
Internal Data Memory, 128 bytes

15. Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.
It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a parity bit, and two user-definable status flags.
The Carry bit, other than serving the functions of a Carry bit in arithmetic operations, also serves as the “Accumulator” for a number of Boolean operations.
the Auxiliary Carry for BCD operations.
The bits RS0 and RS1 are used to select one of the four register banks shown below. A number of instructions refer to these RAM locations as R0 through R7. The selection of which of the four banks is being referred to is made on the basis of the bits RS0 and RS1 at execution time.
The parity bit reflects the number of 1’s in the Accumulator: P = 1 if the Accumulator contains an odd number of 1’s, and P = 0 if the Accumulator contains an even number of 1’s.
Two bits in the PSW are uncommitted and may be used as general purpose status flags.

17. Interrupt Structure The 8051 provides 4 interrupt sources
Two external interrupts
Two timer interrupts
Additional description follows in Operations chapter

18. Port Structures The 8051 contains four I/O ports
All four ports are bidirectional
Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer
Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory
Accessing external memory works like this
Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte being written or read)
Port 2 outputs the high byte (only needed when the address is 16 bits wide)
Port 3 pins are multifunctional. The alternate functions are activated with the 1 written in the corresponding bit in the port SFR

20. Read-Modify-Write Feature
When reading a port some instructions read the latch and others read the pin
The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called “read-modify-write” instructions

21. Timer/Counters The 8051 has two 16-bit Timer/Counter registers Timer 0
Both can work either as timers or event counters
Both have four different operating modes from which to select.
Mode 0 (13-bit Timer)
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with Auto-Reload)
Mode 3 (Two 8-bit Timers)

22. Instruction Set Optimized for 8-bit control applications
Fast addressing modes for accessing internal RAM in order to facilitate byte operations on small data structures
Good for systems that require a lot of Boolean processing because of its extensive support for one-bit variables as a separate data type

23. Addressing Modes (1/3) Direct Addressing Indirect Addressing
Operand is specified by an 8-bit address field in the instruction
This address mode is possible only for addressing internal Data RAM and SFRs
Indirect Addressing
The instruction specifies a register which contains the address of the operand
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer
The address register for 16-bit addresses can only be 16-bit “data pointer” register, DPTR
Both internal and external RAM can be indirectly addressed

24. Addressing Modes (2/3) Register Instructions
Special instructions are used for accessing four register banks (containing R0 to R7)
This instructions have 3-bit register specification within the opcode
This way of accessing registers is much more efficient because of no need for the address byte
When such instruction is executed one of registers in selected ban is accessed
Register bank is selected by two bank select bits in PSW

25. Addressing Modes (3/3) Register-Specific Instructions
These are instructions which are specific to a certain register and they don’t need an address byte (they always operate with the same register)
Immediate Constants
The value of a constant follows the opcode
MOV A, #10 – loads the Accumulator with the decimal number 10
Indexed Addressing
Only Program Memory can be accessed and it can be a read
Used for reading look-up tables in Program Memory and “case jump” instruction

26. Instruction Types of 8051 Arithmetic Instructions Logical Instructions
Data Transfers
Lookup Tables
Boolean Instructions
Jump Instructions

27. 8051 Registers

28. The Instruction Set and Addressing Modes
Rn Register R7-R0 of the currently selected Register Bank.
direct 8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register,etc.( )].
@Ri 8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0.
#data 8-bit constant included in instruction.
#data bit constant included in instruction.
addr bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte Program Memory address space.
addr bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction.
rel Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
bit Direct Addressed bit in Internal Data RAM or Special Function Register.

29. ARITHMETIC OPERATIONS
ADD A,Rn Add register to Accumulator
ADD A,direct Add direct byte to Accumulator
ADD Add indirect RAM to Accumulator
ADD A,#data Add immediate data to Accumulator
ADDC A,Rn Add register to Accumulator with Carry
ADDC A,direct Add direct byte to Accumulator with Carry
ADDC Add indirect RAM to Accumulator with Carry
ADDC A,#data Add immediate data to Acc with Carry
SUBB A,Rn Subtract Register from Acc with borrow
SUBB A,direct Subtract direct byte from Acc with borrow
SUBB Subtract indirect RAM from ACC with borrow
SUBB A,#data Subtract immediate data from Acc with borrow
INC A Increment Accumulator
INC Rn Increment register
INC direct Increment direct byte
Increment direct RAM
DEC A Decrement Accumulator
DEC Rn Decrement Register
DEC direct Decrement direct byte
Decrement indirect RAM
INC DPTR Increment Data Pointer
MUL AB Multiply A & B
DIV AB Divide A by B
DA A Decimal Adjust Accumulator

30. LOGICAL OPERATION ANL A,Rn AND Register to Accumulator
ANL A,direct AND direct byte to Accumulator
ANL AND indirect RAM to Accumulator
ANL A,#data AND immediate data to Accumulator
ANL direct,A AND Accumulator to direct byte
ANL direct,#data AND immediate data to direct byte
ORL A,Rn OR register to Accumulator
ORL A,direct OR direct byte to Accumulator
ORL OR indirect RAM to Accumulator
ORL A,#data OR immediate data to Accumulator
ORL direct,A OR Accumulator to direct byte
ORL direct,#data OR immediate data to direct byte
XRL A,Rn Exclusive-OR register to Accumulator
XRL A,direct Exclusive-OR direct byte to Accumulator
XRL Exclusive-OR indirect RAM to Accumulator
XRL A,#data Exclusive-OR immediate data to Accumulator
XRL direct,A Exclusive-OR Accumulator to direct byte
XRL direct,#data Exclusive-OR immediate data to direct byte

31. LOGICAL OPERATION CLR A Clear Accumulator CPL A Complement Accumulator
RL A Rotate Accumulator Left
RLC A Rotate Accumulator Left through the Carry
RR A Rotate Accumulator Right
RRC A Rotate Accumulator Right through the Carry
SWAP A Swap nibbles within the Accumulator

32. Data Transfers MOV A,Rn Move register to Accumulator
MOV A,direct Move direct byte to Accumulator
MOV Move indirect RAM to Accumulator
MOV A,#data Move immediate data to Accumulator
MOV Rn,A Move Accumulator to register
MOV Rn,direct Move direct byte to register
MOV Rn,#data Move immediate data to register
MOV direct,A Move Accumulator to direct byte
MOV direct,Rn Move register to direct byte
MOV direct,direct Move direct byte to direct
MOV Move indirect RAM to direct byte
MOV direct,#data Move immediate data to direct byte
Move Accumulator to indirect RAM
Move direct byte to indirect RAM

33. Data Transfers MOV @Ri,#data Move immediate data to indirect RAM
MOV DPTR,#data16 Load Data Pointer with a 16-bit constant
MOVC Move Code byte relative to DPTR to Acc
MOVC Move Code byte relative to PC to Acc
MOVX Move External RAM (8-bit addr) toAcc
MOVX Move External RAM (16-bit addr) to Acc
Move Acc to External RAM (8-bit addr)
Move Acc to External RAM (16-bitaddr)
PUSH direct Push direct byte onto stack
POP direct Pop direct byte from stack
XCH A,Rn Exchange register with Accumulator
XCH A,direct Exchange direct byte with Accumulator
XCH Exchange indirect RAM with Accumulator
XCHD Exchange low-order Digit indirect RAM with Acc

34. BOOLEAN VARIABLE MANIPULATION
CLR C Clear Carry
CLR bit Clear direct bit
SETB C Set Carry
SETB bit Set direct bit
CPL C Complement Carry
CPL bit Complement direct bit
ANL C,bit AND direct bit to CARRY
ANL C,/bit AND complement of direct bit to Carry
ORL C,bit OR direct bit to Carry
ORL C,/bit OR complement of direct bit to Carry
MOV C,bit Move direct bit to Carry
MOV bit,C Move Carry to direct bit
JC rel Jump if Carry is set
JNC rel Jump if Carry not set
JB bit,rel Jump if direct Bit is set
JNB bit,rel Jump if direct Bit is Not set
JBC bit,rel Jump if direct Bit is set & clear bit

35. PROGRAM BRANCHING ACALL addr11 Absolute Subroutine Call
LCALL addr16 Long Subroutine Call
RET Return from Subroutine
RETI Return from interrupt
AJMP addr11 Absolute Jump
LJMP addr16 Long Jump
SJMP rel Short Jump (relative addr)
Jump indirect relative to the DPTR
JZ rel Jump if Accumulator is Zero
JNZ rel Jump if Accumulator is Not Zero
CJNE A,direct,rel Compare direct byte to Acc and Jump if Not Equal
CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal
CJNE Rn,#data,rel Compare immediate to register and Jump if Not Equal
Compare immediate to indirect and Jump if Not Equal
DJNZ Rn,rel Decrement register and Jump if NotZero
DJNZ direct,rel Decrement direct byte and Jump ifNot Zero
NOP No Operation

36. Lookup Tables

37. Timer/Counters 8051 has two 16-bit Timer/Counter registers
These registers can be used as timers or as event counters
When operating as a timer, the timer/counter runs for a programme length of time, then issues an interrupt request.
When operating as a counter, the timer/counter counts negative transitions on an external pin. After a preset number of counts, the counter issues an interrupt request.
Both registers have additional four operating modes

38. Timer/Counter Modes
The selection for “Timer” or “Counter” is done by control bits C/T in the TMOD register
Both Timer/Counters have four operating modes, which Modes 0, 1 and 2 are the same for both Timer/Counters, Mode 3 is different
Modes are selected by bit pairs (M1, M0) in TMOD SFR
Another SFR used for work with Timer/Counters is TCON containing flag (TFx) and control (TRx) bits

39. TMOD REGISTER

40. T CON REGISTER

43. Timer 0
Timer 0 functions as either a timer or event counter in four modes of operation. Timer 0 is controlled by the four lower bits of the TMOD register (see Table 2-5) and bits 0, 1, 4 and 5 of the TCON register (see Table 2-3). TMOD register selects the method of timer gating (GATE0), timer or counter operation (T/C0#) and mode of operation (M10 and M00). The TCON register provides timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating an interrupt request.
It is important to stop timer/counter before changing mode.

44. Mode 0 (13-bit Timer)
Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register) and the lower five bits of the TL0 register. The upper three bits of TL0 register are indeterminate and should be ignored.
Pre scalar overflow increments the TH0 register. As the count rolls over from all 1’s to all 0’s, it sets the timer interrupt flag TF0. The counted input is enabled to the Timer when TR0 = 1 and either GATE = 0 or INT0 = 1.
(Setting GATE = 1 allows the Timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the Special Function register TCON, GATE is in TMOD.
Mode 0 operation is the same for Timer 0 as for Timer 1. Substitute TR0, TF0 and INT0 for the corresponding Timer 1 signals. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

45. Mode 1 (16-bit Timer)
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16
bits. Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in cascade. The selected input increments the TL0 register.

46. Mode 2 (8-bit Timer with Auto-Reload)
Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the TH0 register. TL0 overflow sets TF0 flag in the TCON register and reloads TL0 with the contents of TH0, which is preset by software.
When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to the TH0 register.
Mode 2 operation is the same for Timer/Counter 1.

47. Mode 3 (Two 8-bit Timers)
Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers.
This mode is provided for applications requiring an additional 8-bit timer or counter. TL0 uses the timer 0 control bits C/T0# and GATE0 in the TMOD register, and TR0 and TF0 in the TCON register in the normal manner.
TH0 is locked into a timer function (counting FPER /6) and takes over use of the timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of timer 1 is restricted when timer 0 is in mode 3.

48. Interrupt 8051 provides 4 interrupt sources
2 external interrupts
2 timer interrupts
They are controlled via two SFRs, IE and IP
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE (Interrupt Enable). IE also exists a global disable bit, which can be cleared to disable all interrupts at once

49. Interrupt
Each interrupt source can also be individually set to one of two priority levels by setting or clearing a bit in IP (Interrupt Priority)
A low-priority interrupt can be interrupted by high-priority interrupt, but not by another low-priority one
A high-priority interrupt can’t be interrupted by any other interrupt source
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced, so within each priority lever there is a second priority structure

50. Interrupt
This internal priority structure is determined by the polling sequence, shown in the following table

51. External Interrupts
External interrupts ~INT0 and ~INT1 have two ways of activation
Level-activated
Transition-activated
This depends on bits IT0 and IT1 in TCON
The flags that actually generate these interrupts are bits IE0 and IE1 in TCON
On-chip hardware clears that flag that generated an external interrupt when the service routine is vectored to, but only if the interrupt was transition-activated
When the interrupt is level-activated, then the external requesting source is controlling the request flag, not the on-chip hardware

52. Timer 0 and Timer 1 Interrupts
Timer interrupts are generated by TF0 and TF1 flags in their respective Timer/Counter registers
Similarly like in the case of transition-activated external interrupts, the flag that generated an interrupt is cleared by the on-chip hardware when the service routine is vectored to

53. Handling of Interrupts
When interrupt occurs (or correctly, when the flag for an enabled interrupt is found to be set 1), the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some other conditions block the interrupt
Several conditions can block an interrupt
An interrupt of equal or higher priority level is already in progress
The current (polling) cycle is not the final cycle in the execution of the instruction in progress
The instruction in progress is RETI or any write to IE or IP registers
If an interrupt flag is active but not being responded to for one of the above conditions, must be still active when the blocking condition is removed, or the denied interrupt will not be serviced
Next step is saving the registers on stack. The hardware-generated LCALL causes only the contents of the Program Counter to be pushed onto the stack, and reloads the PC with the beginning address of the service routine
In some cases it also clears the flag that generated the interrupt, and in other cases it doesn’t. It clears an external interrupt flag (IE0 or IE1) only if it was transition-activated.

54. Handling of Interrupts
Having only PC be automatically saved gives programmer more freedom to decide how much time to spend saving other registers. Programmer must also be more careful with proper selection, which register to save
The service routine for each interrupt begins at a fixed location. The interrupt locations are spaced at 8-byte interval, beginning at 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1 and 001BH for Timer 1, shown in the following tables
Execution of service routine continues from that
location until the end, that is until it encounters RETI.
RETI instruction does two things
It informs the processor that this interrupt
Routine is finished
Secondly, reloads the PC from the top bytes
from the stack

55. Reset The reset input is RST pin
To accomplish a reset the RST pin must be held high for at least two machine cycles
In the response on the RST signal, CPU generates an internal reset
The external reset signal is asynchronous to the internal clock
In the internal reset algorithm, 0s are written to all the SFRs except the port latches and Stack Pointer
The port latches are initialized to FFH and Stack Pointer to 07H
Driving ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state
The internal RAM is not affected by reset. On power up the RAM content is indeterminate

56. IE: Interrupt Enable Register (bit addressable)
If the bit is 0, the corresponding interrupt is disabled. Otherwise, the interrupt is enabled.

57. IP: Interrupt Priority Register (bit addressable)
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the interrupt has a higher priority

58. 8051 CONNECTION TO RS232 RxD and TxD pins in the 8051
8051 has two pins used for transferring and receiving data serially
TxD and RxD are part of the port 3 group
pin 11 (P3.1) is assigned to TxD
pin 10 (P3.0) is designated as RxD
these pins are TTL compatible
require a line driver to make them RS232 compatible
driver is the MAX232 chip

59. 8051 CONNECTION TO RS232
MAX232
converts from RS232 voltage levels to TTL voltage levels
uses a +5 V power source
MAX232 has two sets of line drivers for transferring and receiving data
line drivers used for TxD are called T1 and T2
line drivers for RxD are designated as R1 and R2
T1 and R1 are used together for TxD and RxD of the 8051
second set is left unused.
MAX233
MAX233 performs the same job as the MAX232
eliminates the need for capacitors
much more expensive than the MAX232

60. 8051 CONNECTION TO RS232 Figure (a) Inside MAX232
(b) its Connection to the 8051 (Null Modem)

61. 8051 CONNECTION TO RS233 Figure (a) Inside MAX233
(b) Its Connection to the 8051 (Null Modem)

62. 8051 SERIAL PORT PROGRAMMING IN ASSEMBLY
Baud rate in the 8051
serial communications of the 8051 with the COM port of the PC
must make sure that the baud rate of the 8051 system matches the baud rate of the PC's COM port
baud rate in the 8051 is programmable
done with the help of Timer 1
relationship between the crystal frequency and the baud rate in the 8051
8051 divides the crystal frequency by 12 to get the machine cycle frequency
XTAL = MHz, the machine cycle frequency is kHz
8051's UART divides the machine cycle frequency of kHz by 32 once more before it is used by Timer 1 to set the baud rate
921.6 kHz divided by 32 gives 28,800 Hz
Timer 1 must be programmed in mode 2, that is 8-bit, auto-reload

63. 8051 SERIAL PORT PROGRAMMING IN ASSEMBLY
Timer 1 TH1 Register Values for Various Baud Rates

64. machine cycle frequency Timer 1 frequency provided by 8051 UART
With XTAL = MHz, find the TH1 value needed to have the following baud rates. (a) 9600 (b) 2400 (c) 1200
machine cycle frequency
= MHz / 12 = kHz
Timer 1 frequency provided by 8051 UART
= kHz / 32 = 28,800 Hz
(a) 28,800 / 3 = 9600 where -3 = FD (hex)
(b) 28,800 / 12 = 2400 where -12 = F4 (hex)
(c) 28,800 / 24 = 1200 where -24 = E8 (hex)

65. 8051 SERIAL PORT PROGRAMMING IN ASSEMBLY
MHz
XTAL oscillator

66. 8051 SERIAL PORT PROGRAMMING IN ASSEMBLY
SBUF (serial buffer) register
A byte of data to be transferred via the TxD line must be placed in the SBUF registerSBUF holds the byte of data when it is received by the RxD line
can be accessed like any other register
MOV SBUF,#'D' ;load SBUF=44H, ASCII for 'D‘
MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator
when a byte is written, it is framed with the start and stop bits and transferred serially via the TxD pin
when the bits are received serially via RxD, it is deframe by eliminating the stop and start bits, making a byte out of the data received, and then placing it in the SBUF

67. 8051 SERIAL PORT PROGRAMMING IN ASSEMBLY
SCON (serial control) register
to program the start bit, stop bit, and data bits
SCON Serial Port Control Register (Bit-Addressable)

68. SERIAL PORT PROGRAMMING IN ASSEMBLY
SM0 and SM1 determine the mode
only mode 1 is important
For mode 1 SM0= 0, SM1=1
when mode 1 is chosen, the data framing is 8 bits, 1 stop bit, and 1 start bit
compatible with the COM port of PCs
mode 1 allows the baud rate to be variable and is set by Timer 1 of the 8051
for each character a total of 10 bits are transferred, where the first bit is the start bit, followed by 8 bits of data, and finally 1 stop bit.

69. SERIAL PORT PROGRAMMING IN ASSEMBLY
REN (receive enable)
REN=1, allows 8051 to receive data on the RxD
if 8051 is to both transfer and receive data, REN must be set to 1
REN=0, the receiver is disabled
TI (transmit interrupt)
when 8051 finishes the transfer of the 8-bit character, it raises the TI flag to indicate that it is ready to transfer another byte
RI (receive interrupt)
when the 8051 receives data serially via RxD, it places the byte in the SBUF register
then raises the RI flag bit to indicate that a byte has been received and should be picked up before it is lost

70. Program to transfer data serially
TMOD register is loaded with the value 20H
TH1 is loaded with value to set the baud rate
SCON register is loaded with the value 50H
TR1 is set to 1 to start Timer1
TI is cleared by the "CLR TI" instruction
transmit character byte is written into the SBUF register
TI flag bit is monitored to see if the character has been transferred completely
to transfer the next character, go to Step 5.
program to transfer letter "A" serially at 4800 baud

71. Write a program to transfer the message "YES" serially at 9600 baud, 8-bit data, 1 stop bit. Do this continuously.

72. PROGRAMMING IN ASSEMBLY
Importance of the TI flag
check the TI flag bit, we know whether can transfer another byte
TI flag bit is raised by the 8051
TI flag cleared by the programmer
writing a byte into SBUF before the TI flag bit is raised, may lead to loss of a portion of the byte being transferred
Program to receive data serially
TMOD register is loaded with the value 20H
TH1 is loaded with value set the baud rate
SCON register is loaded with the value 50H
TR1 is set to 1 to start Timer 1
RI is cleared with the "CLR RI" instruction
RI flag bit is monitored to see if an entire character has been received yet
RI=1 SBUF has the byte, its contents are moved into a safe place
to receive the next character, go to Step 5

73. Program the 8051 to receive bytes of data serially, and put them in P1
Program the 8051 to receive bytes of data serially, and put them in P1. Set the baud rate at 4800, 8-bit data, and 1 stop bit.

74. Importance of the RI flag bit
it receives the start bit, next bit is the first bit of the character
when the last bit is received, a byte is formed and placed in SBUF
when stop bit is received, makes RI = 1
when RI=1, received byte is in the SBUF register, copy SBUF contents to a safe place
after the SBUF contents are copied the RI flag bit must be cleared to 0