1. Pugazhendhi.M
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TIMERS
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2. Timer modules Timer module 0 Timer module 1 Timer module 2
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3. TIMER0 MODULE Software selectable as an 8-bit or 16-bit timer/ counter
Readable and writable
Dedicated 8-bit software programmable prescaler
Clock source selectable to be external or internal
Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
Edge select for external clock
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4. TIMER0 CONTROL REGISTER
T0CON:
bit 7 TMR0ON: Timer0 On/Off Control bit
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
bit 5 T0CS: Timer0 Clock Source Select bit
bit 4 T0SE: Timer0 Source Edge Select bit
bit 3 PSA: Timer0 Prescaler Assignment bit
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
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5. TIMER0 OPERATION Operate as a timer or counter
Timer mode is selected by clearing the T0CS bit
Counter mode is selected by setting the T0CS bit
An 8-bit counter is available as a prescaler for the Timer0 module
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6. TIMER1 MODULE
16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L)
Readable and writable (both registers)
Internal or external clock select
Interrupt-on-overflow from FFFFh to 0000h
RESET from CCP module special event trigger
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7. TIMER1 CONTROL REGISTER
T1CON:
bit 7 RD16: 16-bit Read/Write Mode Enable bit
bit 6 Unimplemented: Read as '0'
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
bit 1 TMR1CS: Timer1 Clock Source Select bit
bit 0 TMR1ON: Timer1 On bit
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8. TIMER1 OPERATION Operates as a timer, synchronous counter
and as an asynchronous counter
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output)
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit
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9. TIMER2 MODULE 8-bit timer (TMR2 register) 8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to
generate clock shift
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10. TIMER2 CONTROL REGISTER
T2CON:
bit 7 Unimplemented: Read as '0'
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
bit 2 TMR2ON: Timer2 On bit
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
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11. TIMER2 OPERATION
Timer2 can be used as the PWM time-base for the PWM mode of the CCP module.
The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock.
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12. TIMER3 MODULE
16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L)
Readable and writable (both registers)
Internal or external clock select
Interrupt-on-overflow from FFFFh to 0000h
RESET from CCP module trigger
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13. TIMER3 CONTROL REGISTER
T3CON:
bit 7 RD16: 16-bit Read/Write Mode Enable bit
bit 6-3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
bit 1 TMR3CS: Timer3 Clock Source Select bit
bit 0 TMR3ON: Timer3 On bit
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14. TIMER3 OPERATION Operates as a timer, synchronous counter
and as an asynchronous counter
The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h.
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18. Continue……….
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