Presentation is loading. Please wait.

Presentation is loading. Please wait.

EE201C Chapter 3 Interconnect RLC Modeling

Published byRenée Rochon Modified over 6 years ago

Similar presentations

Presentation on theme: "EE201C Chapter 3 Interconnect RLC Modeling"— Presentation transcript:

1 EE201C Chapter 3 Interconnect RLC Modeling
Prof. Lei He

2 Chapter 3 Interconnect RLC Model
Efficient capacitance model Efficient inductance model RC and RLC circuit model generation I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

3 Reading Assignments J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", ACM/IEEE Design Automation Conference, June 1997, pp L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", (nomination for Best Paper Award)IEEE Custom Integrated Circuits Conference, San Diego, CA, pp , May 1999. M. Xu and L. He, "An efficient model for frequency-based on-chip inductance," IEEE/ACM International Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp , March 2001.

4 Is RC Model still Sufficient?
Interconnect impedance is more than resistance Z  R +jL   1/tr On-chip inductance should be considered When L becomes comparable to R as we move towards Ghz+ designs I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

5 Candidates for On-Chip Inductance
Wide clock trees Skews are different under RLC and RC models Neighboring signals are disturbed due to large clock di/dt noise Fast edge rate (~100ps) buses RC model under-estimates crosstalk P/G grids (and C4 bumps) di/dt noise might overweight IR drop I will first briefly give the background and overview of my dissertation, then cover more details for an important component of the dissertation: the LR-base STIS optimization. Here LR refers to local refinement, and STIS refers to simultaneous transistor and interconnect sizing. Finally, we draw conclusions and discuss future works.

6 Resistance vs Inductance
Length = 2000, Width = 0.8 Thickness = 2.0, Space = 0.8 R and L for a single wire Ls and Lx for two parallel wires

7 Impact of Inductance 6000u 5u 10u 5u Gnd Clk Gnd RC model RLC model

8 Inductance Extraction from Geometries
Numerical method based on Maxwell’s equations Accurate, but way too slow for iterative physical design and verification Efficient yet accurate models Coplanar bus structure [He-Chang-Shen-et al, CICC’99] Strip-lines and micro-strip bus lines [Chang-Shen-He-et al, DATE’2K] Used in HP for state-of-the-art CPU design

9 Definition of Loop Inductance
Ii Ij Vj Vi The loop inductance is

10 Loop Inductance for N Traces
TwL Tw Tw Assume edge traces are AC-grounded leads to 3x3 loop inductance matrix Inductance has a long range effect non-negligible coupling between t1 and t3, even with t2 between them Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR It is not sufficient to consider only a single net, as did by most interconnect modeling and optimization works

11 Table in Brute-Force Way is Expensive
TwL Tw Tw Tw TwR TsL Ts Ts TsR tL t1 t2 t3 tR Self inductance has nine dimensions: (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR) Mutual inductance has ten dimensions: (n, length, location1, location2,TwL,TsL,Tw,Ts,TwR,TsR) Length is needed because inductance is not linearly scalable

12 Definition of Partial Inductance
Vj Vi Partial inductance is the portion of loop inductance for a segment when its current returns via the infinity called partial element equivalent circuit (PEEC) model If current is uniform (no skin effect), the partial inductance is

13 Partial Inductance for N Traces
TwL Tw Tw Tw TwR TsL Ts Ts TsR tL t1 t2 t3 tR Treat edge traces same as inner traces lead to 5x5 partial inductance table Partial inductance model is more accurate compared to loop inductance model Without pre-setting current return loop

14 Foundation I The self inductance under the PEEC model for a trace depends only on the trace itself (w/ skin effect for a given frequency). 6.50 TwL Tw Tw Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR

15 Foundation II The mutual inductance under the PEEC model for two traces depends only on the traces themselves (w/ skin effect for given frequency). 4.66 6.50 6.17 TwL Tw Tw Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR

16 Foundation III The self loop inductance for a trace on top of a ground plane depends only on the trace itself (its length, width, and thickness) TwL Tw Tw Tw TwR TsL Ts Ts TsR tL t1 t2 t3 tR 4.8 tR

17 Foundation IV The mutual loop inductance for two traces on top of a ground plane depends only on the two traces themselves (their lengths, widths, and thickness) TwL Tw Tw Tw TwR Ts Ts TsL TsR tL t1 t2 t3 tR 4.8 0.14 tL tR 0.14 4.8

18 Validation and Implication of Foundations
Foundations I and II can be validated theoretically Foundations III and IV were verified experimentally Problem size of inductance extraction can be greatly reduced w/o loss of accuracy Solve 1-trace problem for self inductance Reduce 9-D table to 2-D table Solve 2-trace problem for mutual inductance Reduce 10-D table to 3-D table

19 Analytical Solutions to Inductance
Not suitable for on-chip interconnects Without considering skin effect and internal inductance Self inductance k=f(w,t) < k < Mutual inductance Inductance is not sensitive to width, thickness and spacing No need to consider process variations for inductance

20 Extension to Random Nets [Xu-HE, GLSVLSI’01]
Mutual inductance Lab = + - Mutual inductance Lm1 Lm2 Lm3 Lm4 a b

21 Accuracy Table versus FastHenry
400 random displaced parallel wires cases

22 Error Distribution 5% most cases
Bigger error only found in smaller inductance values

23 Lm(wire21, wire12) / sqrt(L21 * L12)
Full RLC Circuit Model Ls(wire12) $$ Self inductance $$ L11 N11 N12 val L12 N13 N14 val L21 N21 N22 val L22 N23 N24 val $$ mutual inductance $$ K1 L11 L21 val K2 L12 L22 val K3 L11 L12 val K4 L21 L22 val K5 L11 L22 val K6 L21 L12 val N11 N13 N12 N14 N21 N23 N22 N24 For n wire segments per net RC elements: n self inductance: n mutual inductance: n*(n-1) Lm(wire21, wire12) / sqrt(L21 * L12)

24 Normalized RLC Circuit Model
Ls(net1) $$ Self inductance $$ L11 N11 N12 val L12 N13 N14 val L21 N21 N22 val L22 N23 N24 val $$ mutual inductance $$ K1 L11 L21 val K2 L12 L22 val N11 N13 N12 N14 N21 N23 N22 N24 For n segments per wire RC elements: n Self inductance: n Mutual inductance: n Lm(net1, net2) / sqrt(net1 * net2)

25 Full Versus Normalized
Two waveforms are almost identical Running time: Full seconds Normalized 9.1 seconds

26 Application of RLC model: Shielding Insertion
To decide a uniform shielding structure for a given wide bus Ns: number of signal traces between two shielding traces Ws: width of shielding traces Ws Ws Ws ... ... 1 2 3 Ns 1 2 3 Ns

27 Trade-off between Area and Noise
Total 18 signal traces 2000um long, 0.8um wide separated by 0.8um Drivers x; Receivers -- 40x Power supply: 1.3V Ns Ws Noise(v) Routing Area (um) Wire Area (um) (0.0%) 46.4(0.0%) (13%) 50.4(8.8%)

28 Conclusions Inductance is a long-range effect
Inductance can be extracted efficiently use PEEC model Normalized RLC circuit model with a much reduced complexity can be used for buses Full RLC circuit model should be used for random nets Model reduction or sparse inductance model may reduce circuit complexity RLC circuit model may be simulated for interconnect optimization

Download ppt "EE201C Chapter 3 Interconnect RLC Modeling"

Similar presentations

EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.

EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.
Caleb Serafy and Ankur Srivastava Dept. ECE, University of Maryland

Caleb Serafy and Ankur Srivastava Dept. ECE, University of Maryland
Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.
UCLA Modeling and Optimization for VLSI Layout Professor Lei He

UCLA Modeling and Optimization for VLSI Layout Professor Lei He
Transmission Line Network For Multi-GHz Clock Distribution Hongyu Chen and Chung-Kuan Cheng Department of Computer Science and Engineering, University.

Transmission Line Network For Multi-GHz Clock Distribution Hongyu Chen and Chung-Kuan Cheng Department of Computer Science and Engineering, University.
1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.

1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.
Computer Science & Engineering Department University of California, San Diego SPICE Diego A Transistor Level Full System Simulator Chung-Kuan Cheng May.

Computer Science & Engineering Department University of California, San Diego SPICE Diego A Transistor Level Full System Simulator Chung-Kuan Cheng May.
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.

Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.
EE466: VLSI Design Lecture 11: Wires

EE466: VLSI Design Lecture 11: Wires
EE 447 VLSI Design Lecture 5: Wires. EE 447VLSI Design 6: Wires2 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering.

EE 447 VLSI Design Lecture 5: Wires. EE 447VLSI Design 6: Wires2 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering.
Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.

Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.
Weiping Shi Department of Computer Science University of North Texas HiCap: A Fast Hierarchical Algorithm for 3D Capacitance Extraction.

Weiping Shi Department of Computer Science University of North Texas HiCap: A Fast Hierarchical Algorithm for 3D Capacitance Extraction.
Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation Supported by NSF & MARCO GSRC Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego.

Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation Supported by NSF & MARCO GSRC Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego.
The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic.

The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic.
Hao Yu and Lei He Electrical Engineering Dept. UCLA

Hao Yu and Lei He Electrical Engineering Dept. UCLA
Primary Contributions  Derive inversion based VPEC (Vector Potential Equivalent Circuit) model from first principles.  Replace inductances with effective.

Primary Contributions  Derive inversion based VPEC (Vector Potential Equivalent Circuit) model from first principles.  Replace inductances with effective.
Constructing Current-Based Gate Models Based on Existing Timing Library Andrew Kahng, Bao Liu, Xu Xu UC San Diego

Constructing Current-Based Gate Models Based on Existing Timing Library Andrew Kahng, Bao Liu, Xu Xu UC San Diego
04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, 4.4.1-4.4.4 (2 nd edition)

04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.

Similar presentations

Ads by Google