1. Implementing Combinational and Sequential Logic in VHDL
ECE 448
Lab 2
Implementing Combinational and Sequential Logic in VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Agenda for today Part 1: Introduction to Lab 2
Implementing Combinational and Sequential
Logic in VHDL
Part 2: Lab 2 Exercise
Part 3: Lab 1b Demos

3. Part 1 Introduction to Lab 2
ECE 448 – FPGA and ASIC Design with VHDL

4. Stream Cipher PCFB: Encryption
Task 1
Stream Cipher PCFB: Encryption

5. Block vs. stream ciphers
M1, M2, …, Mn
m1, m2, …, mn
Internal state - IS
Block
cipher K K
Stream
cipher
C1, C2, …, Cn
c1, c2, …, cn
Ci=fK(Mi)
ci = fK(mi, ISi) ISi+1=gK(mi, ISi)
Every block of ciphertext
is a function of the current block
of message and the current internal state
of the cipher
Every block of ciphertext
is a function of only one
corresponding block of message

6. A typical stream cipher
Sender
Receiver
Initialization
Vector (IV)
Initialization
Vector (IV)
key
key
Pseudorandom
Keystream
Generator
Pseudorandom
Keystream
Generator ki
keystream ki
keystream mi ci ci mi
message
ciphertext
ciphertext
message

7. CFB (Cipher FeedBack) Mode
A method for turning an arbitrary
block cipher into a stream cipher
Notation:
EK – Block Cipher Encryption with the key K

8. Cipher Feedback Mode - CFB
Encryption IV
. . . EK EK EK EK EK
. . . k1 k2 k3
kN-1 kN m1 m2 m3
mN-1 mN c1 c2 c3
cN-1 cN
ci = mi  ki
ki =EK(ci-1) for i=1..N, and c0 = IV

9. Cipher Feedback Mode - CFB
Decryption IV
. . . EK EK EK EK EK
. . . k1 k2 k3
kN-1 kN m1 m2 m3
mN-1 mN c1 c2 c3
cN-1 cN
mi = ci  ki
ki =EK(ci-1) for i=1..N, and c0 = IV

10. Cipher Feedback Mode - CFBIV IV 1
ISi L 1
ISi L IN IN EK EK
IS1 = IV
ci = EK(ISi)  mi
ISi+1 = ci
OUT
OUT 1 L 1 L ci ci mi mi

11. j-bit Cipher Feedback Mode - CFBIV IV
shift
shift
L-j bits
j bits
L-j bits
j bits 1
L-j L 1
L-j L IN IN EK EK
OUT
OUT
j bits
L-j bits
j bits
L-j bits 1 j L 1 j L ci ci mi mi

12. Stream Cipher PCFB: Block Diagram
iv_reg EK
p_out
msg_reg
d_in

13. Stream Cipher PCFB: Block DiagramEK
iv_reg
p_out
msg_reg
d_in

14. Notation

15. Stream Cipher PCFB: Block Diagram
iv_reg
p_out
msg_reg
d_in

16. Expected Waveform

17. Expected Timing Waveforms
Given
Expected Timing Waveforms
Deliverables
RTL VHDL code for the encryption unit of the stream cipher PCFB.
2. Testbench for the encryption unit of the stream cipher PCFB.
3. Vivado Simulator waveforms obtained by applying your testbench (in the PDF format).

18. Stream Cipher PCFB: Decryption
Bonus Task 1
Stream Cipher PCFB: Decryption

19. Deliverables
Block diagram of the module capable of performing both the encryption and decryption operations of PCFB (depending on the value of the control input decrypt)
RTL VHDL code for the encryption/decryption unit of the stream cipher PCFB.
Testbench for the encryption/decryption unit of the stream cipher PCFB.
4. Vivado Simulator waveforms obtained by applying your testbench (in the PDF format).

20. & Rising Edge Detector (RED)
Task 2
Debouncer
& Rising Edge Detector (RED)

21. Debouncing Buttons key bounce tBOUNCE key bounce tBOUNCE pulse width
Bouncing period typically smaller than 10 ms.
Pulse width typically greater than ms.

22. Using Debouncer & Rising Edge Detector to Generate Short Pulses (1)
DEBOUNCE_RED: Block Diagram
RED – Rising Edge Detector

23. Using Debouncer & Rising Edge Detector to Generate Short Pulses (2)

24. DEBOUNCE_RED: Interface

25. DEBOUNCER: Interface
DEBOUNCER
reset
output
input
clk

26. DEBOUNCER: Block Diagram

27. k and DD Generics
k - width of the counter used to measure the debouncing period
DD - debouncing period in clock cycles
Values of generics given on the next slide assume that the
clock frequency = 100 MHz
and thus
clock period = 10 ns.

28. k and DD Generics Option 1 (value used for simulation only): DD = 100
assuming bouncing period < 1 μs = 1000 ns
condition: DD*10ns = 1000 ns => DD = 100
k=7 because 2^7 > 100
Option 2 (values used for synthesis, implementation,
and experimental testing):
DD =
assuming bouncing period = 10 ms
condition: DD*10ns = 10ms => DD = 1,000,000
k=20 because 2^20 > 1,000,000

29. Rising Edge Detector - RED
Turns a step function into a pulse
Allows a step to drive the circuit for only one clock cycle

30. Rising Edge Detector: Block Diagram
input
clk
output
rising edge detector
reset q
clk
input q
output

31. Given Deliverables Testbench: debounce_red_tb.vhd
1. RTL VHDL code for DEBOUNCE_RED unit.
2. ModelSim Intel FPGA waveforms obtained by applying your testbench (in the PDF format).

32. Comparing Vivado Simulator with ModelSim Intel FPGA
Task 3
Comparing Vivado Simulator
with ModelSim Intel FPGA

33. Be ready to demonstrate using both simulators:
Adding signals to the Waveform window.
Including signals from lower levels of hierarchy.
Using all options to run Simulation.
Introducing Breakpoints and showing the execution of logic before and after a breakpoint in the Waveform window.
Measuring time intervals.
Dealing with Buses (Expanding and viewing all bits of a signal).
Taking a signal and changing Radix to Decimal, Binary and Hexadecimal.
Saving timing waveforms in Native format of the simulators.
Printing output of the simulators to PDF files.
Clearing waveforms.

34. Part 2
Lab 2 Exercise
ECE 448 – FPGA and ASIC Design with VHDL

35. ALU: Interface

37. ALU: Block Diagram

39. Part 3
Lab 1b Demos
ECE 448 – FPGA and ASIC Design with VHDL