1. Operating Systems: A Modern Perspective, Chapter 4

2. Computer Organization4
Computer Organization
Operating Systems: A Modern Perspective, Chapter 4

3. Operating System and Computer Organization
Organization of Conventional Computers
The ALU
The Control Unit
The Memory Unit
I/O Devices
Interrupts
Multiprocessors and Parallel Computers
Operating Systems: A Modern Perspective, Chapter 4

4. Stored Program Computers and Electronic Devices
Pattern
Jacquard Loom
Variable Program
Stored Program Device
Fixed Electronic Device
Operating Systems: A Modern Perspective, Chapter 4

5. Program Specification
Source
int a, b, c, d;
. . .
a = b + c;
d = a - 100;
; Code for a = b + c
load R3,b
load R4,c
add R3,R4
store R3,a
; Code for d = a - 100
load R4,=100
subtract R3,R4
store R3,d
Assembly Language
Operating Systems: A Modern Perspective, Chapter 4

6. Operating Systems: A Modern Perspective, Chapter 4
Machine Language
Assembly Language
; Code for a = b + c
load R3,b
load R4,c
add R3,R4
store R3,a
; Code for d = a - 100
load R4,=100
subtract R3,R4
store R3,d …1 …0 …0 …1 …0 …1
Machine Language
Operating Systems: A Modern Perspective, Chapter 4

7. The von Neumann Architecture
Central Processing Unit (CPU)
Arithmetical Logical Unit
(ALU)
Control Unit
(CU)
Address Bus
Data Bus
Device
Primary
Memory Unit
(Executable
Memory)
Operating Systems: A Modern Perspective, Chapter 4

8. Conventional Computer Organization
Programs and data are brought into the machine from the external; world using I/O devices.
Some of the devices are storage devices. These are used to store info for an indefinite period of time.
When the program and data are ready to be used, they are copied into the main memory
Once the program has been loaded in main memory, the CPU execute the program instruction by instruction
All units are connected using a bus:
address bus
data bus
control circuit to arbitrate access to the bus and control bus operations
other wires are used to various other purposes (e.g. interrupt signals)
All Von Neumann computers have a CPU, with an ALU and a control unit, a primary memory, and a set of I/O devices.
Operating Systems: A Modern Perspective, Chapter 4

9. Operating Systems: A Modern Perspective, Chapter 4
The ALU
load R3,b
load R4,c
add R3,R4
store R3,a
Right Operand
Left Operand R1 R2
. . . Rn
Functional Unit
Status Registers
Result
To/from Primary Memory
Operating Systems: A Modern Perspective, Chapter 4

10. Operating Systems: A Modern Perspective, Chapter 4
Control Unit
load R3,b
load R4,c
add R3,R4
store R3,a …1 …0 …0 …1
Fetch Unit
Decode Unit
Execute Unit PC IR
Control Unit
3046
3050
3054
3058
3050
load R4, c
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4

11. Control Unit Operation
Fetch phase: Instruction retrieved from memory
Execute phase: ALU op, memory data reference, I/O, etc.
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
IR = memory[PC]; // fetch phase };
Operating Systems: A Modern Perspective, Chapter 4

12. Operating Systems: A Modern Perspective, Chapter 4
Memory Unit
Main (Primary) Memory holds both program and data while they are being executed by CPU.
The main memory interface consists of the registers: MAR, MDR, CMD.
Unit of information accessed depends on the width of memory and width of data bus.
Max. addressing space depends on width of address bus.
One request at a time.
CPU and I/O devices may contend for memory access.
Operating Systems: A Modern Perspective, Chapter 4

13. Operating Systems: A Modern Perspective, Chapter 4
Primary Memory Unit
1234
1. Load MAR with address
MAR 1 2
98765
3. Data will then appear in the MDR
MDR
Command
read
2. Load Command with “read”
1234
98765
Read Op:
n-1
Operating Systems: A Modern Perspective, Chapter 4

14. Operating Systems: A Modern Perspective, Chapter 4
I/O devices
Each I/O device consists of a device controller and the physical device itself.
Devices:
- storage devices: for permanent storage (e.g. disk, tape)
- communication devices: to transfer data from the computer to another machine (e.g. keyboard, a terminal display, or a serial port to a modem or a network).
Operating Systems: A Modern Perspective, Chapter 4

15. Operating Systems: A Modern Perspective, Chapter 4
I/O Devices (cont.)
Device controller: hardware that connects the device to the computer.
continuously monitors and controls the operation of the device.
provides an interface to the computer.
The device communicates with the computer via a communication point called a port.
Since several devices need to be connected to a computer, they are connected trough the bus.
Operating Systems: A Modern Perspective, Chapter 4

16. The Device-Controller-Software Relationship
Abstract I/O
Machine
Device manager
Program to manage device controller
Supervisor mode software
Application
Program
Software in the CPU
Device Controller
Device
Operating Systems: A Modern Perspective, Chapter 4

17. Device Controller Interface
busy done
idle
finished
working
(undefined)
. . .
busy
done
Error code
. . .
Command
Status
Data 0
Data 1
Logic
Data n-1
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18. Operating Systems: A Modern Perspective, Chapter 4
I/O Devices (cont.)
How does the computer communicate with an I/O device?
device controller has a set of registers: Command reg., Status reg., Data regs., Address regs, etc.
Status reg.: tells the computer the status of device: idle, busy, non functional, etc.
A process can request an operation from device by placing a command in device’s Command reg.
Data regs. Are used to exchange data
Address regs: used to indicate address of source/destination
Operating Systems: A Modern Perspective, Chapter 4

19. Performing a Write Operation
while(deviceNo.busy || deviceNo.done) <waiting>;
deviceNo.data[0] = <value to write>
deviceNo.command = WRITE;
while(deviceNo.busy) <waiting>;
deviceNo.done = FALSE;
Devices much slower than CPU
CPU waits while device operates
Would like to multiplex CPU to a different process while I/O is in process
Operating Systems: A Modern Perspective, Chapter 4

20. Operating Systems: A Modern Perspective, Chapter 4
Polling I/O …
// Start the device
While((busy == 1) || (done == 1))
wait();
// Device I/O complete
done = 0;
Software
busy
done …
while((busy == 0) && (done == 1))
wait();
// Do the I/O operation
busy = 1;
Hardware
Operating Systems: A Modern Perspective, Chapter 4

21. Operating Systems: A Modern Perspective, Chapter 4
CPU-I/O Overlap …
Ready Processes
CPU
Device …
Ready Processes
I/O Operation
CPU
Device …
Ready Processes
Uses CPU
CPU
Device
Operating Systems: A Modern Perspective, Chapter 4

22. Operating Systems: A Modern Perspective, Chapter 4
I/O Devices (cont.)
How does the computer operate on device controller registers? How does it identify each device?
1. Instruction set of the CPU may have special instructions to operate on I/O devices. E.g.
Input DeviceN, DeviceRegisterN, Rn Output Rn, DeviceN, DeviceRegisterN
etc.
2. Memory Mapped I/O
Operating Systems: A Modern Perspective, Chapter 4

23. Operating Systems: A Modern Perspective, Chapter 4
Memory Mapped I/O
A set of memory addresses are reserved for I/O devices. E.g: 0000 to 3FF in Intel 8086
each device is assigned a sub-set of memory addresses.
A memory address is assigned to each register of each device controller
regular CPU instructions are used to interact with device controller.
Operating Systems: A Modern Perspective, Chapter 4

24. Operating Systems: A Modern Perspective, Chapter 4
Addressing Devices
Primary
Memory
Primary
Memory
Memory Addresses
Device 0
Memory Addresses
Device 0
Device 1
Device 1
Device Addresses
Device n-1
Device n-1
Operating Systems: A Modern Perspective, Chapter 4

25. Operating Systems: A Modern Perspective, Chapter 4
I/O Devices (cont.)
How does the CPU know when a device controller has completed the requested operation?
1. Polling: CPU continually check status register of device controller
2. Interrupt driven I/O: device controller sends a signal to CPU through the bus.
bus must support interrupts
CPU must include an interrupt flag
CPU instruction set must include instructions to test and set/clear interrupt flag.
Operating Systems: A Modern Perspective, Chapter 4

26. Determining When I/O is Complete
CPU
Interrupt Pending
Device
Device
Device
CPU incorporates an “interrupt pending” flag
When device.done  TRUE, interrupt pending flag is set
Hardware “tells” OS that the interrupt occurred
Interrupt handler part of the OS makes process ready to run
Operating Systems: A Modern Perspective, Chapter 4

27. Control Unit with Interrupt (Hardware)
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
if(InterruptRequest) {
/* Interrupt the current process */
/* Save the current PC in address 0 */
memory[0] = PC;
/* Branch indirect through address 1 */
PC = memory[1]; };
memory[1] contains the address of the interrupt handler
Operating Systems: A Modern Perspective, Chapter 4

28. Interrupt Handler (Software)
saveProcessorState();
for(i=0; i<NumberOfDevices; i++)
if(device[i].done) goto deviceHandler(i);
/* something wrong if we get to here … */
deviceHandler(int i) {
finishOperation();
returnToScheduler(); }
Operating Systems: A Modern Perspective, Chapter 4

29. Operating Systems: A Modern Perspective, Chapter 4
A Race Condition
saveProcessorState() {
for(i=0; i<NumberOfRegisters; i++)
memory[K+i] = R[i];
for(i=0; i<NumberOfStatusRegisters; i++)
memory[K+NumberOfRegisters+i] = StatusRegister[i]; }
PC = <machine start address>;
IR = memory[PC];
haltFlag = CLEAR;
while(haltFlag not SET) {
execute(IR);
PC = PC + sizeof(INSTRUCT);
if(InterruptRequest && InterruptEnabled) {
disableInterupts();
memory[0] = PC;
PC = memory[1]; };
Operating Systems: A Modern Perspective, Chapter 4

30. Revisiting the trap Instruction (Hardware)
executeTrap(argument) {
setMode(supervisor);
switch(argument) {
case 1: PC = memory[1001]; // Trap handler 1
case 2: PC = memory[1002]; // Trap handler 2
. . .
case n: PC = memory[1000+n];// Trap handler n };
The trap instruction dispatches a trap handler routine atomically
Trap handler performs desired processing
“A trap is a software interrupt”
Operating Systems: A Modern Perspective, Chapter 4

31. The Trap Instruction Operation
Mode S 1
Branch Table 2
trap 3
Trusted
Code
User
Supervisor
Operating Systems: A Modern Perspective, Chapter 4

32. Direct Memory Access (DMA)
With direct I/O: The CPU is used to move data between a device controller and memory.
The device driver copies the data from the device controller's data registers to main memory.
Note: The device driver runs on the CPU
Operating Systems: A Modern Perspective, Chapter 4

33. Operating Systems: A Modern Perspective, Chapter 4
Direct I/O
Example: An application reads a block from disk
Application asks the OS which asks the device manager which asks the device driver which asks the device controller to read a block of data from disk into memory
disk address, memory address, and size of block
device controller reads block from disk into its internal buffer.
when done, device controller causes an interrupt.
after a context switch, device driver transfers data from controller's buffer into memory one byte/word at a time by executing a loop.
Operating Systems: A Modern Perspective, Chapter 4

34. Direct Memory Access (DMA)
For high speed I/O devices, CPU spends a lot of its time transferring data between I/O devices and memory
Direct Memory Access (DMA): a method used to avoid holding the CPU when transferring large amounts of data.
When a read is issued to a device controller that uses DMA, Device driver gives device controller (1) source disk address, (2) destination memory address, and (3) number of bytes/words in block.
Device controller reads block from disk into its internal buffer.
Device controller transfers block one byte/word at a time to main memory.
When transfer is complete, controller raises an interrupt.
Operating Systems: A Modern Perspective, Chapter 4

35. Direct Memory Access (cont.)
DMA controllers improve performance by increasing overlap between CPU and I/O operations
A DMA controller needs to have:
additional registers to hold memory address and size of bock
logic circuitry to be able to access memory and perform the transfer
CPU and DMA controllers compete for system bus and for access to main memory.
Operating Systems: A Modern Perspective, Chapter 4

36. Operating Systems: A Modern Perspective, Chapter 4
Direct Memory Access
Primary
Memory
Primary
Memory
CPU
CPU
Controller
Controller
Device
Device
Operating Systems: A Modern Perspective, Chapter 4

37. Intel System Initialization
RAM
Boot Prog
ROM
Loader
Power Up
Boot Device
POST OS
BIOS
CMOS …
Hardware Process
Data Flow
Operating Systems: A Modern Perspective, Chapter 4

38. Operating Systems: A Modern Perspective, Chapter 4
How does it all start?
When the computer is started, the control unit branches to a fixed memory location; e.g. initial PC value hardwired.
The fixed location is a ROM address that contains a small bootstrap loader.
The bootstrap loader may be comprehensive enough to load the nucleus of the OS; Otherwise, it loads a loader program that does so.
Once bootstrap phase is done, any program can be run by loading it in memory and loading its initial address in the PC (fetch-decode-exec algorithm)
Operating Systems: A Modern Perspective, Chapter 4

39. Operating Systems: A Modern Perspective, Chapter 4
Bootstrapping
Bootstrap loader (“boot sector”) 1
Fetch Unit
Decode Unit
Execute Unit … PC IR
BIOS loader 0x 0x
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4

40. Operating Systems: A Modern Perspective, Chapter 4
Bootstrapping
Bootstrap loader (“boot sector”) 1 0x 2
BIOS loader 0x
Fetch Unit
Decode Unit
Execute Unit … PC IR 0x
Loader
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4

41. Operating Systems: A Modern Perspective, Chapter 4
Bootstrapping
Bootstrap loader (“boot sector”) 1 0x 2
BIOS loader 0x
Fetch Unit
Decode Unit
Execute Unit … PC IR 0x
Loader 3
0x000A000 OS
Primary Memory
Operating Systems: A Modern Perspective, Chapter 4

42. Operating Systems: A Modern Perspective, Chapter 4
Bootstrapping
Bootstrap loader (“boot sector”) 1 0x 2
BIOS loader 0x 0x
Fetch Unit
Loader 3 PC
000A000
0x000A000
Decode Unit OS IR …
Primary Memory
Execute Unit
4. Initialize hardware
5. Create user environment
6. …
Operating Systems: A Modern Perspective, Chapter 4

43. A Bootstrap Loader Program
FIXED_LOC: // Bootstrap loader entry point
load R1, =0
load R2, =LENGTH_OF_TARGET
// The next instruction is really more like
// a procedure call than a machine instruction
// It copies a block from FIXED_DISK_ADDRESS
// to BUFFER_ADDRESS
read BOOT_DISK, BUFFER_ADDRESS
loop: load R3, [BUFFER_ADDRESS, R1]
store R3, [FIXED_DEST, R1]
incr R1
bleq R1, R2, loop
br FIXED_DEST
Operating Systems: A Modern Perspective, Chapter 4

44. A Pipelined Function Unit
Operand 1
Function Unit
Result
Operand 2
(a) Monolithic Unit
Operand 1
Result
Operand 2
(b) Pipelined Unit
Operating Systems: A Modern Perspective, Chapter 4

45. Operating Systems: A Modern Perspective, Chapter 4
Pipelining
For example, addition can be split up into:
Fetch the operands from memory
Compare exponents
shift one operand
add
Normalize the result
store result in memory
Operating Systems: A Modern Perspective, Chapter 4

46. Operating Systems: A Modern Perspective, Chapter 4
Pipeline Space-Time Diagram
Operating Systems: A Modern Perspective, Chapter 4
5.7

47. Pipelining execution of codes
float x[100], y[100], z[100];
for (i = 0; i < 100; i++)
z[i] = x[i] + y[i];
Vectorization:
(Fortran 90)
z(1:100) = x(1:100) + y(1:100)
Operating Systems: A Modern Perspective, Chapter 4

48. Operating Systems: A Modern Perspective, Chapter 4
Virtue and drawbacks
Well understood, codes are easy to write
Drawbacks:
Need to keep the pipeline full - don’t work well for irregular structures or branches
don’t scale well - upmost speedup is limited by the number of units
Operating Systems: A Modern Perspective, Chapter 4

49. Operating Systems: A Modern Perspective, Chapter 4
A SIMD Machine
ALU
Control
Unit
(a) Conventional Architecture
ALU
Control
Unit
ALU
ALU …
ALU
(b) SIMD Architecture
Operating Systems: A Modern Perspective, Chapter 4

50. Operating Systems: A Modern Perspective, Chapter 4
SIMD systems
A single CPU devoted exclusively to control
a large collection of subordinate ALUs
In each instruction cycle:
instruction is broadcast to all ALUs
each ALU either executes the instruction or is idle
Operating Systems: A Modern Perspective, Chapter 4

51. Operating Systems: A Modern Perspective, Chapter 4
An example
for (i = 0; i < 1000; i++)
if (y[i] != 0.0)
z[i] = x[i]/y[i];
else
z[i] = x[i];
Time Step 1. Test local_y != 0.0.
Time Step 2.
A. If local_y was nonzero, z[i] = x[i]/y[i].
B. If local_y was zero, do nothing.
Time Step 3.
A. If local_y was non zero, do nothing.
B. local_y was zero, z[i] = x[i].
Operating Systems: A Modern Perspective, Chapter 4

52. Operating Systems: A Modern Perspective, Chapter 4
Pros and cons
Many processes will remain idle if there are many conditional branches
easy to program
scale well
SIMD machine examples
Connection machines (Thinking Machines): CM-1, CM-2
MP-2 (Maspar)
Operating Systems: A Modern Perspective, Chapter 4

53. Operating Systems: A Modern Perspective, Chapter 4
A MIMD Machine
Tightly-coupled
Loosely-coupled … P1 Pn P1 Pn … M1 Mk
Network … M1 Mk
Network
Multi-processor System
Multi-computer System
Operating Systems: A Modern Perspective, Chapter 4