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Neil Goldsman and Akin Akturk
CPU Power Neil Goldsman and Akin Akturk
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Task I: Coupled Modeling of Time-Dependent Full-Chip IC and Quantum Non-Isothermal Device Operation
Pentium III Pentium III Temperature
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Motivation : Objective :
As devices get smaller on-chip thermal effects become increasingly important. Predictions indicate that chip temperatures will increase exponentially beyond acceptable values. Thus modeling of full-chip heating is essential for the design of fail-safe architectures in both 2D and 3D. Objective : Develop heating models for 2D and 3D IC’s. Predict circuit and chip performance variations due to chip heating. Test the model and develop temperature sensors by fabricating specially designed chips.
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Functional Blocks in Pentium III
% Area % Power 0 Bus Interface Unit 1 Clock 2 L1 Data Cache 3 Memory Order Buffer 4 Execute 5 L2 Data Cache 6 Register Alias Table 7 Issue 8 Fetch 9 Decode Source:
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Thermal Network Containing Millions of Nodes
MOSFET devices and their thermal connections KCL-type lumped thermal network Pentium has 40 million nodes Thermal Network Containing Millions of Nodes
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Schrödinger Eqn. Poisson Eqn. Electron Current Continuity Eqn. Hole Current Continuity Eqn. Heat flow Eqn. Device Equations
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Integrated Circuit Heat Flow Equation
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Coupled Flowchart Flowchart
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MOSFET IV Curves for T=300K and 400K; VGS=0.4, 0.7, 1.0V
Temperature profile in the channel of a MOSFET; Far left and right corners are source and drain sides, respectively. Far side is parallel to gate terminal. Device Simulations
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Chip Simulations & Cooling with Thermal Contacts
Maximum chip temperature for different device counts with constant power density. Temperature profile for a 0.5cm IC with uniform device activity throughout the chip: Temperature Isotherms range from 300K at the chip edges to 360K inside chip. Maximum chip temperature as a function of uniformly distributed thermal contacts. Thermal contacts cool chip
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Calculated Temperature Profile for Pentium III
Calculated Pentium III Temperature Profile with non-uniform device activity throughout the chip but with uniform device activity within each functional block: Temperature Isotherms range from 300K at the chip edges to 340K inside the clock. Clock and L2 Cache are the hottest and coolest regions, respectively.
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