1. Day 26: November 11, 2011 Memory Overview
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 26: November 11, 2011
Memory Overview
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2. Today Memory Project 2 is on this (posted)
Motivation
Organization
Basic components
Optimization concerns
Project 2 is on this (posted)
Not looked at midterms  try for Monday
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3. Know how to store state
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4. Register Storage Could just put together a large number of registers
Concerns?
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5. Concerns? Large number of wires May want to store for many cycles
Could determine area
5l wire pitch  how wide?
May want to store for many cycles
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6. Usage Scenario How many state values read on each cycle?
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7. Concerns? Large number of wires May want to store for many cycles
Could determine area
May want to store for many cycles
Not able to update all on every cycle
Not able to use all on every cycle
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8. Limited Data Use
What else do we need to share the wires if can only use one register on each cycle?
Use with shared data path
Need to select the one output
Can only update one
Need to control which one gets written
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9. Limited Data Use Add load enable to register
Logic to enable one register on write
Mux to select output
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10. Good Solution? Could get away with just latch
Not full register with master/slave latch
Pay large amount for decode and mux
Proportional to memory bits
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11. Memory Idea Maximize storage density (bits/cm2)
By minimizing the size/complexity of the repeated element
Use shared periphery circuits to provide full functionality
Trades off bandwidth (concurrent access) to save area
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12. Memory Bank
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13. Share Address Decode Word – group of bits read/written together
All have same control
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14. Share Address Decode Words Mux select bits (words) from row read
When only want a subset
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15. Share Address Decode
Result: only spend N0.5 area (perimeter) on selecting rather than linear in bits
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16. Gate Density When is 14n > 6n+32*sqrt(n) ?
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17. Memory Row Use shared enable for wire economy Word line
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18. Memory Column Use shared bus for area and wire economy
Row enable selects the cells to read/write from bus
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19. Memory Cell Hold data Conditionally drive onto output bus
Conditionally overwritten with data from bus
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20. SRAM Memory bit
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21. SRAM Memory bit Core is back-to-back inverters for storage
Like static latch
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22. SRAM Memory bit Core is back-to-back inverters for storage
Like static latch
To minimize size, doesn’t include disable
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23. SRAM Memory bit Pass gate mux for output to column Bit-Line (BL)
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24. SRAM Memory bit How do we write into this cell?
No directionality to pass gate
If drive BL strong enough, can flip value in selected cell
Ratioed operation
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25. Column Capacitance What is capacitance of bit line (column)?
Waccess (M5,M6) – transistor width of column device
d rows
g=Cdiff/Cgate
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26. Time Driving Bit Line In terms of Waccess, Wbuf (M1,M3), d
For Waccess=Wbuf=1, d=512, g=0.5
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27. Column Capacitance Consequence
Want Waccess, Wbuf small to keep memory cell small
Increasing Waccess, also increases Cbl
Don’t really win by sizing up
Driving bit line will be slow
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28. Column Sensing Speedup read time by sensing limited swing
Sense circuit detects small change in bit line voltage(s)
Precharge to intermediate voltage
BL and /BL swing opposite directions
Amplifies for output
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29. Output Amps
Bottom of array includes Sense Amplifiers from bit lines to output
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30. Column Write Writes driven from outside array Use large driver
Strong enough to flip memory bit
Strong so can charge column quickly
Disable when not write
Be careful on your project2
Could overwrite wrong row
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31. Complete Memory Bank
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32. Admin Project 2 out Andre away on Tuesday Due November 23
Note recommend milestones
Andre away on Tuesday
No office hour Tuesday
Will be back for Wednesday lecture
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33. Idea Memory for compact state storage Share circuitry across many bits
Minimize area per bit  maximize density
Aggressively use:
Pass transistors, Ratioing
Precharge, Amplifiers
to keep area down
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