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Integration of cache System into MIPS Pipeline

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1 Integration of cache System into MIPS Pipeline
Data-path control unit design Pipeline stalls on cache misses 2018/11/13 \course\cpeg323-08F\Topic7d

2 Actions Needed on an Instruction-Cache Miss
Send the value of PC-4 to the memory. Instruct main memory to perform a read and wait for the memory to complete its access. Write the cache entry, putting the data from memory in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on. Restart the instruction execution at the first step, which will re-fetch the instruction, this time finding it in the cache. For Data-Cache Miss is essentially identical: On a miss, we simply stall the processor until the memory responds with the data 2018/11/13 \course\cpeg323-08F\Topic7d

3 \course\cpeg323-08F\Topic7d
Cases of Study FastMATH Processor DEC Station 3100 Separate I-Cache and D-Cache. 64kB each one with a one-word block. “Write-through” policy. One-word-line simplifies write-miss handling. Separate I-Cache and D- Cache. 16kB each one with 16-word block. Both “write-through” and “write-back” policies, leaving it up to the operating system to decide which strategy to use for an application. 2018/11/13 \course\cpeg323-08F\Topic7d

4 How to Handle Read/Write on DEC Station 3100
Write: Write-through for both write hit/miss Index the cache using bits of the address. Write both the tag portion (using bits of the address) and the data portion with the word. Also write the word to main memory using the entire address. Very simple but it does not provide very good performance 2018/11/13 \course\cpeg323-08F\Topic7d

5 Miss rates for FastMATH processor for SPEC2000 benchmarks.
See P&H Fig rd Ed or th Ed The combined miss rate is the effective miss rate seen for the combination of the 16 KB instruction cache and 16 KB data cache. It is obtained by weighting the instruction and data individual miss rates by the frequency of instruction and data references. 2018/11/13 \course\cpeg323-08F\Topic7d

6 Combined I-Cache/D-Cache?
Miss ratio: Combined may be better In DECStation 3100 Split Cache (Weighted between Data and Instruction): 5.4% Combined Cache: 4.8% In FastMATH Split Cache (Weighted between Data and Instruction): 3.24% Combined Cache: 3.18% MissI-Cache*IReferences + Miss D-Cache*D References I References + D References #Total-Main-M # Total References Miss Split= MissComb.= Bandwidth considerations 2018/11/13 \course\cpeg323-08F\Topic7d

7 \course\cpeg323-08F\Topic7d
High-Bandwidth Design Alternatives The primary method of achieving higher memory bandwidth is to increase the physical or logical width of the memory system. See P&H Fig rd Ed or th Ed A memory where all components are one word wide A wider memory, bus, and cache. A narrow bus and cache with an interleaved memory. 2018/11/13 \course\cpeg323-08F\Topic7d

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