1. VGA INTERFACE Ly Le Department of Electrical Engineering
University of Washington
EE 590
12/07/2004

2. Contents VGA System Inputs/Outputs System Design Current Stage
Overview of the system
VGA Signals
Signal Timing
System Inputs/Outputs
System Design
Current Stage
Future Plan
Summary

3. Overview of VGA Video graphics array display
Graphically display nodes and direction of the tracking target in the local area tracking system (LATS)
1 tracking point and 4 nodes

4. 5 standard VGA signals

5. VGA Signal Timing 640*480 mode display 25Mhz pixel clock
60Hz refresh frequency

6. System Inputs/Outputs
Information from UARTS showing the location of node tracked from LATS
Outputs: five output signals
Horizontal Sync
Vertical Sync
Red
Green
Blue
Red, Green, Blue either all ones or zeros for black and white colors

7. System Design
High Level Block Diagram

8. System Design (cont.)

9. System Design (cont.) Need ~ 5MB SRAM for video display data
8 bits/pixel
640 x 480 x 8 bits ~ 2.5MB
2.5MB used for current display data
2.5MB used for updated data

10. Current Stage (cont.) Timing control is very critical for HS and VS
Have to understand executable time of instructions
While(1) – 60ns
XGpio_mSetDataReg(XPAR_MYGPIO_BASEADDR, (Xuint32)Value); ns
HS and VS signals controlled by delay_cycle() function
// 60 ns delay for each cycle at 50MHz processor
void delay_cycle(int num_cycle) {
int loop_cnt = 0;
for (loop_cnt = 0; loop_cnt < num_cycle loop_cnt++); }
Ex: if num_cycle = 3, then the delay will be 180ns

11. Current Stage (cont.)
HS and VS Signals

12. Current Stage (cont.)
Difficult to control timing of HS and VS using delay_cycle() function when the program gets bigger and more complicated.
Receive data from RS232
Update data in SRAM
Display video data at 60Hz refresh frequency

13. Future Plan
Design an external counter for HS, VS, and display time intervals
Design an external RS232 system
Use RS232 interrupt to receive the data
Use Microblaze processor for
Handle RS232 interrupt
Manipulate data received from RS232
Control the external RAM (write, address offsets)

14. Summary VGA Interface System System Design
Current Stage and Future Plan