1. Figure 1 PC Emulation System Display Memory [Embedded SOC Software]
SOC RTL
Protocol Interface
MMC
Keypad
Terminal
Transactor C Interface
Transactor HW Interface
Protocol Interface
Terminal
Transactor C Interface
Transactor HW Interface
Protocol Interface
Display
Camera
Transactor C Interface
Transactor HW Interface
Protocol Interface
Camera
Transactor C Interface
Transactor HW Interface
Protocol Interface
Keypad
Ethernet
USB
Transactor C Interface
Transactor HW Interface
Protocol Interface
USB
Transactor C Interface
Transactor HW Interface
Protocol Interface
Ethernet
Audio
Transactor C Interface
Transactor HW Interface
Protocol Interface
Audio
Files
Transactor C Interface
Transactor HW Interface
Protocol Interface
I/O Files
Software Test Environment
Interface Hardware
SoC Prototype

2. ZeBu HW/SW Co-Verification Platform
Figure 2
ZeBu HW/SW Co-Verification Platform
ZeBu Compilation Flow
PC / Linux
PCI
I/F
ZeBu
Test
Environment
DUT
[RTL]
DUT Logic
Emulation
Resources
Up to 64 Xilinx V2-8000
Memory
Server
Clock
Server
Cycle-Based
Verilog/VHDL
RAM
FPGA
Synthesis
ASIC
Synthesis
C/C++
SystemC
Signals
Reconfigurable
Test Bench (RTB)
ZeBu
Compiler
Vectors
DUT Compilation
Embedded Test Bench
Transaction-Based
Hard
Cores
RTB Generation TX RX
Hardware Transactors
C/C++
Logic
Analyzer
Dynamic
Traces
SystemC
Channels
Xilinx P&R
Xilinx P&R
Xilinx P&R
Some of the resources on the ZeBu card are dedicated to map the design under test or DUT. They include two Virtex-II 6000 or 8000 FPGA’s and 128 megabit of static RAM chips.
Everything else on the ZeBu card is dedicated to the RTB. Through the RTB, ZeBu communicates to a software test environment that includes any combination of cycle-based and/or transaction-based test benches, such as HDL simulators, C/C++/SystemC models, Instruction-set-simulators, or even test vectors for regression testing.
The uniqueness of the RTB is the ability to support concurrent processes.
For example, you can connect ZeBu to an HDL simulator to execute a Verilog test bench, and at the same time to an ATM C++ model that communicates at the transaction-level. Concurrently to the above, you may run a software debugger on top of an ARM ISS model.
Through the RTB, ZeBu can also interface to a hardware-based test environment that may consist of synthesizable test benches and/or a target system for in-circuit emulation or ICE. In the latter case, the connections are carried out via an external pod called Z-IcePod. The Z-IcePod also supports hard macros like ARM, MIPS, PowerPCs, etc.
An embedded logic analyzer is also included in the package.
SW Debuggers
RTB
Config Files
DUT
Config Files
In-Circuit Emulation
with Target System