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History of Embedded Systems
Discussion 0.1
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The First Point-Contact Transistor 1947
Bell Labs Museum The First Point-Contact Transistor 1947
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The First Junction Transistor 1951
Bell Labs The First Junction Transistor 1951 M1752 Outside the Lab Lab model
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Texas Instrument’s First IC -- 1958
Jack Kilby Robert Noyce Fairchild Intel
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A single-purpose, programmable, digital system
Embedded System A single-purpose, programmable, digital system
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1961 – Unimate Robot at GM
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1965: PDP-8 first mass-produced Mini
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Electronics, Volume 38, Number 8, April 19, 1965
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Moore’s law Wow This growth rate is hard to imagine, most people underestimate How many ancestors do you have from 20 generations ago i.e., roughly how many people alive in the 1500’s did it take to make you? 220 = more than 1 million people
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Graphical illustration of Moore’s law
1981 1984 1987 1990 1993 1996 1999 2002 10,000 transistors 150,000,000 transistors Leading edge chip in 1981 Leading edge chip in 2002 Something that doubles frequently grows more quickly than most people realize! A 2002 chip can hold about 15, chips inside itself
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1968 – Apollo Guidance Computer
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Intel 4004 source: Computer Museum
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January 1975 cover of Popular Electronics
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1978 – Industrial Holographics
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Time's Man of the Year (1982)
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1985 – Motorola introduces the 68HC11 microcontroller
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1997 – Motorola introduces the 68HC12/HCS12 microcontroller
Additional PWM and CAN interfaces
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Develops WHYP – a subroutine-threaded Forth for the 68HC12
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Chuck Moore, the inventor of Forth, reading Haskell’s WHYP book
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1975 – Signetics invents the FPLA
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1978 – MMI introduces the PAL
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1983 – AMD introduces the 22V10 1984 – Lattice introduces the GAL – an electrically erasable PAL
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1985 – Xilinx introduces the LCA (Logic Cell Array)
The Xilinx XC3000 CLB (configurable logic block).
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1991 – Xilinx introduces the XC4000 Architecture
Programmable Interconnect I/O Blocks (IOBs) XC4003 contained 440,000 transistors 0.7-micron process Configurable Logic Blocks (CLBs)
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XC4000E/X Configurable Logic Blocks
D Q SD RD EC S/R Control 1 F' G' H' DIN H Func. Gen. G F G4 G3 G2 G1 F4 F3 F2 F1 C4 C1 C2 C3 K YQ Y XQ X H1 DIN S/R EC 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset
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Look Up Tables Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: Look Up Table 4-bit address Combinatorial Logic A B C D Z A B C D Z 4 (2 ) 2 = 64K ! Capacity is limited by number of inputs, not complexity Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM G Func. Gen. G4 G3 G2 G1 WE
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1998 – Xilinx introduces the Virtex®™ FPGA family
0.25-micron process
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2003 – Xilinx introduces the Spartan®™-3 family of products
This very low-cost product is the world's first 90nm FPGA 2003 – Xilinx introduces the Spartan®™-3 family of products Very low cost World’s first 90 nm FPGA
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Xilinx will release the world’s first
one-billion transistor device this year x
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Logic Implementations
Fixed (ASICs) -- $12 billion market Programmable (PLDs) -- $3.5 billion market CPLDs FPGAs
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Advantages of ASICs Lower costs for very large volumes
Highest performance capabilities
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Advantages of PLDs Flexibility during design cycle
Available – no long lead times No NRE costs Low inventory Can be modified after delivery
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PLD and ASIC cost cross-over point
Nick Tredennick Gilder Technology Report
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PLD and ASIC cost cross-over points (dots) with time
Nick Tredennick Gilder Technology Report
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